This preview has intentionally blurred sections. Sign up to view the full version.View Full Document
Unformatted text preview: Bus Mechanisms: Totem Pole, Open Collector, . .. More:. .. Finite State Machines: Transition Tables and Transition Diagrams Timing Diagrams Mealey and Moore Machines Building Blocks: S-R Latches Edge Triggered Devices Flip-Flops (D, T, JK) MUXes, deMUXes (selectors) Counters PALs Internal Architecture: SP realization Clock and OE realizations Don't worry about specifics for specific parts VHDL: Understand logical assignment, instantiation IF/Then/Else and Case/When statement structures Entity and Architecture...
View Full Document
- Fall '02
- Logic, Boolean Algebra, Diagrams Timing Diagrams, diagrams Combinational Logic, asynchronous logic Timing