l10 - 6.111 Lecture # 10 Topics for today: Some more...

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Positive Edge Triggered devices Often call it /CLK because setup is when the clock signal is LOW 6.111 Lecture # 10 Topics for today: Some more details of VHDL and more examples Shift Register (as in the 74LS194) Note Lab 2 design should be done by Wednesday Page 1 VHDL Identifiers Case InsenSitivE (but best not to rely on this) First character must be a letter. Letters, Digits, and Underscores (only) Two underscores in succession are not allowed. The last character cannot be an underscore. Using reserved words is NOT allowed. Later versions of emacs use color to distinguish reserved words (and other things) Using reserved words usually provokes an understandable error comment. Legal Examples CLK, Three_StateEnable, h23, Reg_12 Illegal Examples _clk, 3_State_Enable, large#num, clk_, Three__State, register, begin Page 3 But first,… clock Conventions This is only a convention but it is widely used. What is important is when devices are triggered. Setup time here Setup time here Positive Edge Triggered devices Most registers are like this Negative Edge Triggered devices Often call it CLK because setup is when the clock signal is HIGH J-K flip flops tend to be like this Page 2 VHDL Reserved Words Some are abs access after begin± array disconnect file± guarded impure postponed± rem unaffected wait± There are 97: too many to remember! This is another good reason for "incremental" compilation. Start with something that compiles and add code a block at a time Page 4
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VHDL Values: Defined in IEEE 1164. Values you are most likely to use are '0', '1', '-', 'Z' '-' (hyphen) is 'don't care' 'Z' (MUST Be upper case) is 'High Impedance' Vectors are strings Remember VHDL is strongly typed: a+b is valid ONLY if a and b have the same length To assign to a one bit longer number (as in to accommodate overflow) c <= ('0' & a) + ('0' & b) and of course c must be defined to be one bit longer than a and b Designation of constants: '-' is a character± "---" is a string (vector) of length 3± & is the concatenation operator: "01" & "111" is "01111" and so is '0' & "1111" Page 5 Packages Here is a very small package construction Entities need not be in the same file as the package declaration. library ieee;
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This note was uploaded on 07/20/2009 for the course ELECTRICAL 6.111 taught by Professor Prof.dontroxel during the Fall '02 term at MIT.

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l10 - 6.111 Lecture # 10 Topics for today: Some more...

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