l11 - 6.111 Lecture # 11 Handshaking Topics for today:...

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6.111 Lecture # 11 Topics for today: Handshaking± 'Concurrent' and 'Sequential' statements± (Another example: a counter) Yet another example: a small ALU Brief discussion of resource usage A Less Elaborate handshake This is often used in things like UARTs which must deal with asynchronous data streams that they do not control Sender stabilizes data and sets DAV Receiver reads data and clears RDAV Sender de-asserts data and clears DAV Typically, sender does not wait for /RDAV before setting new data. This can be used for detecting 'overrun' errors. Page 3 Handshaking Required when multiple lines of input are involved This is a 'full handshake' Note that both positive going and negative going transitions are important in both directions Receiver indicates ready to receive data by setting RDY Sender sets data valid then sets DAV Receiver reads data then clears RDY Sender acknowledges by clearing DAV Page 2 We should be able to describe the sending and receiving agents as simple finite state machines. Here is the FSM at the Sending end: (Full handshake) library ieee; use ieee.std_logic_1164.all; entity fullsend is generic (size: integer := 4); port (rdy, clk : in std_logic; datin : in std_logic_vector(size-1 downto 0);± dav : out std_logic;± datout : out std_logic_vector(size - 1 downto 0));± end fullsend; Page 4
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And here is the FSM for the receiving end: library ieee; use ieee.std_logic_1164.all; entity fullrecv is generic (size: integer := 4); port (dav, rclk : in std_logic; datin : in std_logic_vector(size-1 downto 0);± rdy : out std_logic;± datout : out std_logic_vector(size - 1 downto 0));± end fullrecv; Page 5 architecture behavioral of fullrecv is type StateType is (w_dav, datav, r_rdy, wt_ndav); attribute enum_encoding of StateType: type is "00 01 11 10"; signal state : StateType; begin rdy <= '1' when (state = w_dav) or (state = datav) else '0'; handshake : process(rclk) begin if rising_edge(rclk) then case state is when w_dav => if dav = '1' then state <= datav; else state <= w_dav; end if; when datav => datout <= datin; state <= r_rdy; when r_rdy => state <= wt_ndav; when wt_ndav => if dav = '0' then state <= w_dav; else state <= wt_ndav; end if; end case; end if; end process handshake; end; Page 7 architecture behavioral of fullsend is type StateType is (wt, dat, d_av, r_dy); attribute enum_encoding of StateType: type is "00 01 11 10"; signal state : StateType; begin dav <= '1' when (state = d_av) or (state = r_dy) else '0'; handshake : process(clk) begin if rising_edge(clk) then case state is when wt => if rdy = '1' then state <= dat; else state <= wt; end if; when dat => datout <= datin; state <= d_av; when d_av => state <= r_dy; when r_dy => if rdy = '0' then state <= wt; else state <= r_dy; end if; end case; end if; end process handshake; end; Page 6 Here is an alternative way of writing an emulator for the '163 counter This is a register which can hold 4 bits Counts when P=T=1, holds when P*T=0 Loads data when /LD = 0 Clears data when /CL = 0
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This note was uploaded on 07/20/2009 for the course ELECTRICAL 6.111 taught by Professor Prof.dontroxel during the Fall '02 term at MIT.

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l11 - 6.111 Lecture # 11 Handshaking Topics for today:...

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