negativetrue - Negative True and VHDL Donald E. Troxel...

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Negative True and VHDL Donald E. Troxel January 10, 1999 Revised 01/20/02 Signals in VHDL are inherently positive true. Normally this is not a problem as most signals in digital systems are positive true. That is, a signal is high when it "happens". As such, it is good practice to have the signal without a bubble at the input or output of device or block. It is also good practice to have the signal name without a beginning slash or equivalent beginning to reinforce the fac that the signal is positive true. This is standard with VHDL. Indeed, a slash is not a legal character for use as a signal name. However, sometimes a signal is desired to be negative true. That is, a signal is low when it "happens". As such, it is good practice to have the signal with a bubble at the input or output of a device or block. It is also good practice to have the signal name with a beginning distinctive part such as a slash, or, perhaps, a letter n, or even a syllable such as n_, not_, or neg_true_. For example, the following are good names to use for the signal foo: /foo nfoo n_foo not_foo neg_true_foo The first is impossible since a slash is not a legal character in a VHDL identifier. The second could be troublesome for signals whose names naturally begin with the letter n. Either of the
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This note was uploaded on 07/20/2009 for the course ELECTRICAL 6.111 taught by Professor Prof.dontroxel during the Fall '02 term at MIT.

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negativetrue - Negative True and VHDL Donald E. Troxel...

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