ps3f02 - Massachusetts Institute of Technology Department...

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Massachusetts Institute of Technology Department of Electrical Engineering and Computer Science 6.111 - Introductory Digital Systems Laboratory Problem Set 3 Issued: Lecture 7 Day Due: Lecture 10 Day Problem 1: A finite state machine shown below has one input, X, and one output, Z, and two state variables, A and B, and a clock input. (a) Give the state transition table for this FSM. (b) Draw the state diagram for this FSM. (c) Implement this FSM in VHDL. Hand in your code and a printout of part of your simulation showing the correct operation of the FSM. B A X Z CLK Q’ D Q’ DQ Q
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(d) Fill in the timing diagram below. You may neglect propagation delay in the logic, assuming it to be zero. Problem 2: Design a 3-bit counter that can count either up or down on the rising edge of the clock. There are
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ps3f02 - Massachusetts Institute of Technology Department...

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