ps4f02soln

# ps4f02soln - Massachusetts Institute of Technology...

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Massachusetts Institute of Technology Department of Electrical Engineering and Computer Science 6.111 - Introductory Digital Systems Laboratory Problem Set 4 Solutions Issued: Lecture 12 Day Problem 1: 1) 2) 3) Mealy. S depends on the state and the inputs. xyzsc 00000 00110 01010 01101 10010 10101 11001 11111 inputs: xy output: S 00/0 01/0 10/0 11/1 01/1 10/1 11/0 00/1

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4) After a clock edge, it takes 2 us for the output of the Fip Fop to change. Then 4 us later, the output of the adder changes. This value needs to be held for 2 us to satisfy the setup time of the Fip Fop. Since the contamination delay of each part is at least 2 us, we could have another edge now and the setup time would be satis±ed. So the minimum clock period is 6 us. Problem 2: 1) Below is a truth table that corresponds to the ²SM. The state labels can be mapped to a three bit state variable. All entries not entered below are illegal. state member guest exp token next state open idle 0 0 X X idle 0 idle 0 1 X X guest enters 0 idle 1 0 X X member enters 1 member enters 0 0 0 X wait for guest 0
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ps4f02soln - Massachusetts Institute of Technology...

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