ps5f02soln - Problem Set 5 Solutions library ieee use...

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library ieee; use ieee.std_logic_1164.all; use work.std_arith.all; -- here is the declaration of entity entity la_rewarder is port (clk, go, SRAM_busy, SRAM_rdy: in std_logic; min: buffer std_logic_vector(2 downto 0); max: buffer std_logic_vector(2 downto 0); staff_hours_adr: out std_logic_vector(2 downto 0); staff_hours : in std_logic_vector(2 downto 0); minmax_start, minmax_done : buffer std_logic; timeoff : buffer std_logic_vector(3 downto 0); rdy : out std_logic); end la_rewarder; --the assumption is that the payroll module functions in such way to provide --a signal SRAM_busy to denote that it is updating the system and SRAM_rdy --when the data on the bus is valid (corresponding to the values stored at --staff_hours_adr). -- here is the body of the architecture architecture state_machine of la_rewarder is -- first declaration of all states type StateType is (idle,idle2, rew_LA1, rew_LA12, rew_LA2, rew_LA22, rew_LA3, rew_LA32, rew_LA4, rew_LA42, rew_finish); signal present_state, next_state : StateType; signal LA_points1 : std_logic_vector(1 downto 0); signal LA_points2 : std_logic_vector(1 downto 0); signal LA_points3 : std_logic_vector(1 downto 0); signal LA_points4 : std_logic_vector(1 downto 0); component maxmin port( clk, SRAM_busy, SRAM_rdy : in std_logic; minmax_start : buffer std_logic; min : buffer std_logic_vector(2 downto 0); max : buffer std_logic_vector(2 downto 0); staff_hours : in std_logic_vector(2 downto 0); minmax_done : buffer std_logic); end component; begin process(present_state, clk, min, max, SRAM_busy, go, timeoff, LA_points1, LA_points2, LA_points3, LA_points4, SRAM_rdy, minmax_done,min, max, staff_hours) begin timeoff <= "0000"; --start off with timeoff being zero for all LA's rdy <= '0'; -- start off with the output not calculated minmax_start <= '0'; case present_state is when idle => timeoff <= "0000"; -- in idle, no LA gets time off Problem Set 5 Solutions
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--in idle, any address is asserted rdy <= '0'; --the timeoff is not calculated yet minmax_start <= '0'; if (SRAM_busy = '1') then next_state <= idle; --SRAM_busy means that the payroll is updating the SRAM table --of weekly hours timeoff <= "0000"; rdy <= '0'; elsif (minmax_done = '0' and go <= '1') then --this is the state where the payroll has updated --the records, but the minor fsm --has not calculated the new min and max values; --min and max values have to be --calculated after each payroll update. minmax_start <= '1'; --the major fsm asserts the start signal that the --minor fsm uses to see when it needs --to perform the next calculation. next_state <= idle2; --next_state = wait for minmax to calculate min and rdy <= '0'; --max values no output is ready at this point timeoff <= "0000"; elsif (minmax_done = '1' and go = '1') then --this is the state when the payroll has finished --updating the records and the --minmax has finished calculating the min and max next_state <= rew_LA1; --values next state checks the first LA's points, --LA corresponds to 011 in the table
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This note was uploaded on 07/20/2009 for the course ELECTRICAL 6.111 taught by Professor Prof.dontroxel during the Fall '02 term at MIT.

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ps5f02soln - Problem Set 5 Solutions library ieee use...

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