l7_memory

l7_memory - L7: Memory Basics and Timing Acknowledgements:...

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Unformatted text preview: L7: Memory Basics and Timing Acknowledgements: Materials in this lecture are courtesy of the following people and used with permission. - Rex Min - Rabaey, J., A. Chandrakasan, B. Nikolic. Digital Integrated Circuits: A Design Perspective. Prentice Hall, 2003, chapter 10. L7: 6.111 Spring 2004 Introductory Digital Systems Laboratory 1 Memory Classification & Metrics Read-Write Memory Non-Volatile Read-Write Memory EPROM E2PROM FLASH Read-Only Memory (ROM) Random Access Non-Random Access FIFO LIFO Mask-Programmed SRAM DRAM Key Design Metrics: 1. Memory Density (number of bits/ m2) and Size 2. Access Time (time to read or write) and Throughput 3. Power Dissipation L7: 6.111 Spring 2004 Introductory Digital Systems Laboratory 2 Memory Array Architecture 2L-K Bit Line Storage Cell 2L-K row by K column Mx2 cell array Row Decode AK AK+1 Word Line AL-1 M.2 K Sense Amps/Driver A0 AK-1 Amplify swing to rail-to-rail amplitude Column Decode Input-Output (M bits) Selects appropriate word (i.e., multiplexor) L7: 6.111 Spring 2004 Introductory Digital Systems Laboratory 3 Latch and Register Based Memory Positive Latch Negative Latch D 0 D Q 1 D 1 Q 0 Clk G Register Memory Negative latch Positive latch DQ QM DQ G Q CLK CLK Works fine for small memory blocks (e.g., small register files) Inefficient in area for large memories – density is the key metric in large memory circuits How do we minimize cell size? L7: 6.111 Spring 2004 Introductory Digital Systems Laboratory 4 Static RAM (SRAM) Cell (The 6-T Cell) BL WL VDD M2 M5 Q M1 BL M4 Q M6 BL WL Q WL Q M3 BL Write: set BL and BL to 0 and VDD or VDD and 0 and then enable WL (i.e., set to VDD) Read: Charge BL and BL to VDD and then enable WL (i.e., set to VDD). Sense a small change in BL or BL State held by cross-coupled inverters (M1-M4) Retains state as long as power supply turned on Feedback must be overdriven to write into the memory L7: 6.111 Spring 2004 Introductory Digital Systems Laboratory 5 Interacting with a Memory Device Address Pins Write Logic Write enable Chip Enable Tri-state Driver enable in out Address pins drive row and column decoders Data pins are bidirectional and shared by reads and writes Row Decoder … Memory Matrix Data Pins … Sense Amps/Drivers Column Decoder Read Logic Write enable Output Enable If enable=0 out = Z If enable =1 out = in Output Enable gates the chip’s tristate driver Write Enable sets the memory’s read/write mode Chip Enable/Chip Select acts as a “master switch” 6 L7: 6.111 Spring 2004 Introductory Digital Systems Laboratory MCM6264C 8k x 8 Static RAM On the outside: 13 Same (bidirectional) data bus used for reading and writing Chip Enables (E1 and E2) E1 must be low and E2 must be high to enable the chip 8 Address Chip Enables E1 E2 Write Enable W Output Enable G MCM6264C Data DQ[7:0] Write Enable (W) When low (and chip is enabled), the values on the data bus are written to the location selected by the address bus Output Enable (G) On the inside: A2 A3 A4 A5 A7 A8 A9 A11 Row Decoder DQ[7:0] When low (and chip is enabled), the data bus is driven with the value of the selected memory location E1 E2 Memory matrix 256 rows 32 Column L7: 6.111 Spring 2004 A0 A1 A6 A10 A12 … … Sense Amps/Drivers Column Decoder W G Introductory Digital Systems Laboratory 7 Reading an Asynchronous SRAM Address E1 Access time (from enable low) Address Valid Access time (from address valid) G Bus enable time Bus tristate time Data (Tristate) Data Valid E2 assumed high (enabled), W =1 (read mode) Read cycle begins when all enable signals (E1, E2, G) are active Data is valid after read access time Access time is indicated by full part number: MCM6264CP-12 12ns Data bus is tristated shortly after G or E1 goes high L7: 6.111 Spring 2004 Introductory Digital Systems Laboratory 8 Address Controlled Reads Address Address 1 Address 2 Address 3 Access time (from address valid) Contamination time E1 G Bus enable time Bus tristate time Data 2 Data 3 Data Data 1 E2 assumed high (enabled), W =1 (read mode) Can perform multiple reads without disabling chip Data bus follows address bus, after some delay L7: 6.111 Spring 2004 Introductory Digital Systems Laboratory 9 Writing to Asynchronous SRAM Address E1 Write pulse width Address Valid Address setup time Address hold time W Data setup time Data hold time Data Valid E2 and G are held high Data Data latched when W or E1 goes high (or E2 goes low) Data must be stable at this time Address must be stable before W goes low Write waveforms are more important than read waveforms Glitches to address can cause writes to random addresses! L7: 6.111 Spring 2004 Introductory Digital Systems Laboratory 10 Sample Memory Interface Logic Write cycle Read cycle Clock/E1 G W Address Data Drive data bus only when clock is low Ensures address are Clock stable for writes Control Prevents bus (write, read, reset) contention Write data Minimum clock period Read data is twice memory Address access time Address for write Data for write Write occurs here, when E1 goes high VCC Address for read Data read Data can be latched here FPGA ext_chip_enable ext_write_enable E2 E1 W G Data[7:0] FSM ext_output_enable int_data D Q D Q D Q SRAM ext_data ext_address Address[12:0] L7: 6.111 Spring 2004 Introductory Digital Systems Laboratory 11 Multi-Cycle Read/Write (less aggressive, recommended timing) clk Control (write, read, reset) W_b VDD FSM data_sample int_data D Q Q D G_b data_oen E2 E1 W G SRAM write_data read_data address address_load Data[7:0] ext_data D Q Address[12:0] ext_address write completes read, address is stable address/data stable Data latched into FPGA write states 1-3 read states 1-3 L7: 6.111 Spring 2004 Introductory Digital Systems Laboratory 12 Simulation from Previous Slide write completes read, address is stable address/data stable Data latched into FPGA write states 1-3 read states 1-3 L7: 6.111 Spring 2004 Introductory Digital Systems Laboratory 13 Verilog for Simple Multi-Cycle Access module memtest (clk, reset, G_b, W_b, address, ext_address, write_data, read_data, ext_data, read, write, state, data_oen, address_load, data_sample); input clk, reset, read, write; output G_b, W_b; output [12:0] ext_address; reg [12:0] ext_address; input [12:0] address; input [7:0] write_data; output [7:0] read_data; reg [7:0] read_data; inout [7:0] ext_data; reg [7:0] int_data; output [2:0] state; reg [2:0] state, next; output data_oen, address_load, data_sample; reg G_b, W_b, G_b_int, W_b_int, address_load, data_oen, data_oen_int, data_sample; wire [7:0] ext_data; parameter IDLE = 0; parameter write1 = 1; parameter write2 = 2; parameter write3 = 3; parameter read1 = 4; parameter read2 = 5; parameter read3 = 6; // Sequential always block for state assignment assign ext_data = data_oen ? int_data : 8'hz; always @ (posedge clk) begin if (!reset) state <= IDLE; else state <= next; G_b <= G_b_int; W_b <= W_b_int; data_oen <= data_oen_int; if (address_load) ext_address <= address; if (data_sample) read_data <= ext_data; if (address_load) int_data <= write_data; end // note that address_load and data_sample are not // registered signals 1/4 2/4 L7: 6.111 Spring 2004 Introductory Digital Systems Laboratory 14 Verilog for Simple Multi-Cycle Access // Combinational always block for next-state // computation always @ (state or read or write) begin W_b_int = 1; G_b_int = 1; Setup the address_load = 0; Default values data_oen_int = 0; data_sample = 0; case (state) IDLE: if (write) begin next = write1; address_load = 1; data_oen_int = 1; end else if (read) begin next = read1; address_load = 1; G_b_int = 0; end else next = IDLE; write1: begin next = write2; W_b_int = 0; data_oen_int =1; end write2: begin next = write3; data_oen_int =1; end write3: begin next = IDLE; data_oen_int = 0; end read1: begin next = read2; G_b_int = 0; data_sample = 1; end read2: begin next = read3; end read3: begin next = IDLE; end default: next = IDLE; endcase end endmodule 3/4 4/4 L7: 6.111 Spring 2004 Introductory Digital Systems Laboratory 15 Testing Memories Common device problems Bad locations: rare for individual locations to be bad Slow (out-of-spec) timing(s): access incorrect data or violates setup/hold Catastrophic device failure: e.g., ESD Missing wire-bonds/devices (!): possible with automated assembly Transient Failures: Alpha particles, power supply glitch Common board problems Stuck-at-Faults: a pin shorted to VDD or GND Open Circuit Fault: connections unintentionally left out Open or shorted address wires: causes data to be written to incorrect locations Open or shorted control wires: generally renders memory completely inoperable Approach Device problems generally affect the entire chip, almost any test will detect them Writing (and reading back) many different data patterns can detect data bus problems Writing unique data to every location and then reading it back can detect address bus problems L7: 6.111 Spring 2004 Introductory Digital Systems Laboratory 16 An Approach An idea that almost works 1. 2. 3. 4. 5. Write 0 to location 0 Read location 0, compare value read with 0 Write 1 to location 1 Read location 1, compare value read with 1 … Suppose the memory was missing (or output enable was disconnected) What is the problem? Address Data Control 0 Write 0 0 Read 1 Write 1 1 Read 2 Write 2 2 Read 2 3 2 Read Write Data bus is undriven but wire capacitance briefly maintains the bus state: memory appears to be ok! L7: 6.111 Spring 2004 Introductory Digital Systems Laboratory 17 A Simple Memory Tester Write to all locations, then read back all locations Separates read/write to the same location with reads/writes of different data to different locations (both data and address busses are changed between read and write to same location) • write 8-LSB’s of address <counter> to location specified by address <counter> • Increment counter <counter> = last address? • • • • • • • • Write 0 to address 0 Write 1 to address 1 … Write (n mod 256) to address n Read address 0, compare with 0 Read address 1, compare with 1 … Read address n, compare with (n mod 256) To normal memory interface Comparator • Reset counter Counter • Read address <counter> Matched? • Report success <counter> = last address? Enable memory test SRAM Data Address Control • Compare data read with 8-LSB’s of <counter> • Increment counter Does not match? • Report failure L7: 6.111 Spring 2004 Introductory Digital Systems Laboratory 18 Synchronous SRAM Memories Clocking provides input synchronization and encourages more reliable operation at high speeds Write Logic Write Enable Chip Enable Row Decoder Address Pins Memory matrix difference between read and write timings creates wasted cycles (“wait states”) R1 R2 W3 … Data Pins Read Logic … Sense Amps/Drivers Column Decoder Output Enable long “flow-through” combinational path creates high CLK-Q delay R4 W5 CE WE CLK Address Data L7: 6.111 Spring 2004 A1 A2 Q1 Q2 A3 D3 A4 Q4 A5 D5 Introductory Digital Systems Laboratory 19 ZBT Eliminates the Wait State The wait state occurs because: On a read, data is available after the clock edge On a write, data is set up before the clock edge ZBT (“zero bus turnaround”) memories change the rules for writes On a write, data is set up after the clock edge (so that it is read on the following edge) Result: no wait states, higher memory throughput R1 R2 W3 R4 W5 CE WE CLK Address Data A1 A2 Q1 A3 Q2 Write to A3 requested A4 D3 Data D3 loaded A5 Q4 Write to A5 requested D5 Data D5 loaded L7: 6.111 Spring 2004 Introductory Digital Systems Laboratory 20 Pipelining Allows Faster CLK Pipeline the memory by registering its output Good: Greatly reduces CLK-Q delay, allows higher clock (more throughput) Bad: Introduces an extra cycle before data is available (more latency) Memory matrix ZBT Write Logic Write Enable Chip Enable Row Decoder … Address Pins Data Pins Read Logic Output Enable As an example, see the CY7C147X ZBT Synchronous SRAM … Sense Amps/Drivers Column Decoder pipelining register pipelining register R1 R2 W3 R4 W5 CE WE CLK Address Data L7: 6.111 Spring 2004 A1 A2 one-cycle latency... A3 Q1 A4 Q2 A5 D3 (ZBT write to A3) Q4 D5 (ZBT write to A5) 21 Introductory Digital Systems Laboratory EPROM Cell – The Floating Gate Transistor 20 V 0V 5V [Rabaey03] 5V 10 V S 5V 20 V 5V S 0V 2.5 V S D D D Avalanche injection Removing programming voltage leaves charge trapped Programming results in higher V T . EPROM Cell (Image removed due to copyright considerations.) This is a non-volatile memory (retains state when supply turned off) L7: 6.111 Spring 2004 Introductory Digital Systems Laboratory 22 Interacting with Flash and (E)EPROM Reading from flash or (E)EPROM is the same as reading from SRAM Vpp: input for programming voltage (12V) EPROM: Vpp is supplied by programming machine Modern flash/EEPROM devices generate 12V using an on-chip charge pump EPROM lacks a write enable Not in-system programmable (must use a special programming machine) For flash and EEPROM, write sequence is controlled by an internal FSM Writes to device are used to send signals to the FSM Although the same signals are used, one can’t write to flash/EEPROM in the same manner as SRAM Flash/EEPROM block diagram Address Chip Enable Output Enable Write Enable L7: 6.111 Spring 2004 Vcc (5V) Data Charge pump Programming voltage (12V) FSM Introductory Digital Systems Laboratory EPROM omits FSM, charge pump, and write enable 23 Dynamic RAM (DRAM) Cell WL BL Write "1" Read "1" WL M1 CS X DRAM uses Special Capacitor Structures GND BL VDD VDD/2 sensing CBL VDD /2 Cell Plate Si Refilling Poly [Rabaey03] Capacitor Insulator Storage Node Poly To Write: set Bit Line (BL) to 0 or VDD & enable Word Line (WL) (i.e., set to VDD ) To Read: set Bit Line (BL) to VDD /2 & enable Word Line (i.e., set it to VDD ) Si Substrate 2nd Field Oxide DRAM relies on charge stored in a capacitor to hold state Found in all high density memories (one bit/transistor) Must be “refreshed” or state will be lost – high overhead L7: 6.111 Spring 2004 Introductory Digital Systems Laboratory 24 Asynchronous DRAM Operation Address RAS CAS Data WE (Tristate) Row Col Q (data from RAM) set high/low before asserting CAS RAS-before-CAS for a read or write (Row and column addresses taken on falling edges of RAS and CAS) CAS-before-RAS for a refresh Clever manipulation of RAS and CAS after reads/writes provide more efficient modes: early-write, read-write, hidden-refresh, etc. (See datasheets for details) L7: 6.111 Spring 2004 Introductory Digital Systems Laboratory 25 Addressing with Memory Maps ‘138 is a 3-to-8 decoder Address[12:0] Data[7:0] Address[12:0] Data[7:0] Address[12:0] Data[7:0] 26 Maps 16-bit address space to 8, 13-bit segments Upper 3-bits of address determine which chip is enabled SRAM 1 SRAM 2 EPROM SRAM-like interface is often used for peripherals Output Enable Referred to as “memory mapped” peripherals Write Enable Address[15:0] ~G ~W ~E1 ~G ~W ~E1 [12:0] ‘138 A ~G2B Y5 Y4 Y3 Y2 Y1 Y0 0xFFFF 0xE000 0xDFFF 0xC000 0xBFFF 0xA000 0x9FFF EPROM SRAM 2 SRAM 1 Bus Enable +5V ~G2A G1 Data[7:0] ~G ~W ~E1 Address[2:0] Data[7:0] [2:0] Memory Map 15 14 13 C B Y7 Y6 [12:0] 0x2000 0x1FFF 0x0000 ADC ADC Introductory Digital Systems Laboratory Analog Input L7: 6.111 Spring 2004 [12:0] ~E1 ~G Key Messages on Memory Devices SRAM vs. DRAM SRAM holds state as long as power supply is turned on. DRAM must be “refreshed” – results in more complicated control DRAM has much higher density, but requires special capacitor technology. FPGA usually implemented in a standard digital process technology and uses SRAM technology Non-Volatile Memory Fast Read, but very slow write (EPROM must be removed from the system for programming!) Holds state even if the power supply is turned off Memory Internals Has quite a bit of analog circuits internally -- pay particular attention to noise and PCB board integration Device details Don’t worry about them, wait until 6.012 or 6.374 L7: 6.111 Spring 2004 Introductory Digital Systems Laboratory 27 You Should Understand Why… control signals such as Write Enable should be registered a multi-cycle read/write is safer from a timing perspective than the single cycle read/write approach it is a bad idea to enable two tri-states driving the bus at the same time an SRAM does not need to be “refreshed” while a DRAM does an EPROM/EEPROM/FLASH cell can hold its state even if the power supply is turned off a synchronous memory can result in higher throughput L7: 6.111 Spring 2004 Introductory Digital Systems Laboratory 28 ...
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This note was uploaded on 07/21/2009 for the course EECS 6.111 taught by Professor Prof.ananthachandrakasan during the Spring '04 term at MIT.

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