{[ promptMessage ]}

Bookmark it

{[ promptMessage ]}

l11_12_fpgas - L11/12 Reconfigurable Logic Architectures...

Info iconThis preview shows pages 1–6. Sign up to view the full content.

View Full Document Right Arrow Icon
L11/12: 6.111 Spring 2004 1 Introductory Digital Systems Laboratory L11/12: Reconfigurable Logic L11/12: Reconfigurable Logic Architectures Architectures Acknowledgements: Materials in this lecture are courtesy of the following people and used with permission. Computer Science) - Randy H. Katz (University of California, Berkeley, Department of Electrical Engineering & - Frank Honore http://www.cs.washington.edu/370) - Gaetano Borriello (University of Washington, Department of Computer Science & Engineering,
Background image of page 1

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full Document Right Arrow Icon
L11/12: 6.111 Spring 2004 2 Introductory Digital Systems Laboratory History of Computational Fabrics History of Computational Fabrics Discrete devices: relays, transistors (1940s-50s) Discrete logic gates (1950s-60s) Integrated circuits (1960s-70s) e.g. TTL packages: Data Book for 100’s of different parts Gate Arrays (IBM 1970s) Transistors are pre-placed on the chip & Place and Route software puts the chip together automatically – only program the interconnect (mask programming) Software Based Schemes (1970’s- present) Run instructions on a general purpose core ASIC Design (1980’s to present) Turn Verilog directly into layout using a library of standard cells Effective for high-volume and efficient use of silicon area Programmable Logic (1980’s to present) A chip that be reprogrammed after it has been fabricated Examples: PALs, EPROM, EEPROM, PLDs, FPGAs Excellent support for mapping from Verilog
Background image of page 2
L11/12: 6.111 Spring 2004 3 Introductory Digital Systems Laboratory Reconfigurable Logic Reconfigurable Logic Logic blocks To implement combinational and sequential logic Interconnect Wires to connect inputs and outputs to logic blocks I/O blocks Special logic blocks at periphery of device for external connections Key questions: How to make logic blocks programmable? (after chip has been fabbed!) What should the logic granularity be? How to make the wires programmable? (after chip has been fabbed!) Specialized wiring structures for local vs. long distance routes? How many wires per logic block? Logic Logic Configuration Inputs Outputs n m Q Q SET CLR D
Background image of page 3

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full Document Right Arrow Icon
L11/12: 6.111 Spring 2004 4 Introductory Digital Systems Laboratory Programmable Array Logic (PAL) Programmable Array Logic (PAL) Based on the fact that any combinational logic can be realized as a sum-of-products PALs feature an array of AND-OR gates with programmable interconnect input signals AND array OR array output signals programming of product terms programming of sum terms
Background image of page 4
L11/12: 6.111 Spring 2004 6 Introductory Digital Systems Laboratory Inside the 22v10 “ Inside the 22v10 “ Macrocell Macrocell ” Block
Background image of page 5

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full Document Right Arrow Icon
Image of page 6
This is the end of the preview. Sign up to access the rest of the document.

{[ snackBarMessage ]}