l11_12_fpgas

l11_12_fpgas - L11/12: Reconfigurable Logic Architectures...

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L11/12: 6.111 Spring 2004 1 Introductory Digital Systems Laboratory L11/12: Reconfigurable Logic L11/12: Reconfigurable Logic Architectures Architectures Acknowledgements: Materials in this lecture are courtesy of the following people and used with permission. Computer Science) - Randy H. Katz (University of California, Berkeley, Department of Electrical Engineering & - Frank Honore http://www.cs.washington.edu/370) - Gaetano Borriello (University of Washington, Department of Computer Science & Engineering,
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L11/12: 6.111 Spring 2004 2 Introductory Digital Systems Laboratory History of Computational Fabrics History of Computational Fabrics ± Discrete devices: relays, transistors (1940s-50s) ± Discrete logic gates (1950s-60s) ± Integrated circuits (1960s-70s) ² e.g. TTL packages: Data Book for 100’s of different parts ± Gate Arrays (IBM 1970s) ² Transistors are pre-placed on the chip & Place and Route software puts the chip together automatically – only program the interconnect (mask programming) ± Software Based Schemes (1970’s- present) ² Run instructions on a general purpose core ± ASIC Design (1980’s to present) ² Turn Verilog directly into layout using a library of standard cells ² Effective for high-volume and efficient use of silicon area ± Programmable Logic (1980’s to present) ² A chip that be reprogrammed after it has been fabricated ² Examples: PALs, EPROM, EEPROM, PLDs, FPGAs ² Excellent support for mapping from Verilog
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L11/12: 6.111 Spring 2004 3 Introductory Digital Systems Laboratory Reconfigurable Logic Reconfigurable Logic ± Logic blocks ² To implement combinational and sequential logic ± Interconnect ² Wires to connect inputs and outputs to logic blocks ± I/O blocks ² Special logic blocks at periphery of device for external connections ± Key questions: ² How to make logic blocks programmable? (after chip has been fabbed!) ² What should the logic granularity be? ² How to make the wires programmable? (after chip has been fabbed!) ² Specialized wiring structures for local vs. long distance routes? ² How many wires per logic block? Logic Logic Configuration Inputs Outputs n m Q Q SET CLR D
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L11/12: 6.111 Spring 2004 4 Introductory Digital Systems Laboratory Programmable Array Logic (PAL) Programmable Array Logic (PAL) ± Based on the fact that any combinational logic can be realized as a sum-of-products ± PALs feature an array of AND-OR gates with programmable interconnect input signals AND array OR array output signals programming of product terms programming of sum terms
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L11/12: 6.111 Spring 2004 6 Introductory Digital Systems Laboratory
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This note was uploaded on 07/21/2009 for the course EECS 6.111 taught by Professor Prof.ananthachandrakasan during the Spring '04 term at MIT.

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l11_12_fpgas - L11/12: Reconfigurable Logic Architectures...

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