l3cmbintlverilog

l3cmbintlverilog - L3 Introduction to Verilog...

Info iconThis preview shows pages 1–6. Sign up to view the full content.

View Full Document Right Arrow Icon
L3: Introduction to L3: Introduction to Verilog Verilog (Combinational Logic) (Combinational Logic) Courtesy of Rex Min . Used with permission. Verilog References: Samir Palnitkar, Verilog HDL, Pearson Education (2nd edition). Donald Thomas, Philip Moorby, The Verilog Hardware Description Language, Fifth Edition, Kluwer Academic Publishers. J. Bhasker, Verilog HDL Synthesis (A Practical Primer), Star Galaxy Publishing L3: 6.111 Spring 2004 Introductory Digital Systems Laboratory 1
Background image of page 1

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Synthesis and Synthesis and HDLs HDLs ± Hardware description language (HDL) is a convenient, device- independent representation of digital logic Verilog input a,b; output sum; assign sum <= {1b’0, a} + {1b’0, b}; FPGA PAL ASIC (Custom ICs) Netlist g1 "and" n1 n2 n5 g2 "and" n3 n4 n6 g3 "or" n5 n6 n7 ± HDL description is compiled into a netlist ± Synthesis optimizes the logic ± Mapping targets a specific hardware platform Compilation and Synthesis Mapping L3: 6.111 Spring 2004 Introductory Digital Systems Laboratory 2
Background image of page 2
The FPGA: A Conceptual View The FPGA: A Conceptual View ± An FPGA is like an electronic breadboard that is wired together by an automated synthesis tool ± Built-in components are called macros sel interconnect DQ LUT F(a,b,c,d) G(a,b,c,d) a b c d RAM ADR R/W DATA counter + 32 32 32 SUM (for everything else) L3: 6.111 Spring 2004 Introductory Digital Systems Laboratory 3
Background image of page 3

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Synthesis and Mapping for Synthesis and Mapping for FPGAs FPGAs ± Infer macros: choose the FPGA macros that efficiently implement various parts of the HDL code counter ... always @ (posedge clk) begin count <= count + 1; end ... “This section of code looks like a counter. My FPGA has some of those. ..” HDL Code Inferred Macro ± Place-and-route: with area and/or speed in mind, choose the needed macros by location and route the interconnect M M M M M M M M M M M M M M M M M M M M M M M M M M M M M M M M M M M “This design only uses 10% of the FPGA. Let’s use the macros in one corner to minimize the distance between blocks.” L3: 6.111 Spring 2004 Introductory Digital Systems Laboratory 4
Background image of page 4
Verilog Verilog : The Module : The Module ± Verilog designs consist of interconnected modules . ± A module can be an element or collection of lower level design blocks. ± A simple module with combinational logic might look like this: Out = sel a + sel b 1 0 sel out outbar a b 2-to-1 multiplexer with inverted output module mux_2_to_1(a, b, out, Declare and name a module; list its outbar, sel); ports. Don’t forget that semicolon. // This is 2:1 multiplexor± input a, b, sel;± output out, outbar;± Comment starts with // Verilog skips from // to end of the line Specify each port as input, output, or inout Express the module’s behavior. assign out = sel ? a : b;± Each statement executes in assign outbar = ~out; parallel; order does not matter.
Background image of page 5

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Image of page 6
This is the end of the preview. Sign up to access the rest of the document.

This note was uploaded on 07/21/2009 for the course EECS 6.111 taught by Professor Prof.ananthachandrakasan during the Spring '04 term at MIT.

Page1 / 28

l3cmbintlverilog - L3 Introduction to Verilog...

This preview shows document pages 1 - 6. Sign up to view the full document.

View Full Document Right Arrow Icon
Ask a homework question - tutors are online