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Unformatted text preview: iggered registers are also called flip-flops) this circuit is not clocked and outputs change "asynchronously" with the inputs
L4: 6.111 Spring 2004 Introductory Digital Systems Laboratory 6 Making a Clocked Memory Element: Element: Positive D-Latch Latch D CLK R S Q hold sample hold sample hold D G Q R and S clock clk A Positive D-Latch: Passes input D to output Q when CLK is high and holds state when clock is low (i.e., ignores input D) A Latch is level-sensitive: invert clock for a negative latch
L4: 6.111 Spring 2004 Introductory Digital Systems Laboratory 7 Multiplexor Based Positive & Negative Latch Latch 2:1 multiplexor
in0 in1 0 out 1 D SEL 0 Q 1 D 1 Q 0 Positive Latch Negative Latch Out = sel * in1 + sel * in0 CLK CLK clk clk
"data" "load" "remember" "stored value" L4: 6.111 Spring 2004 Introductory Digital Systems Laboratory 8 Building an Edge-Triggered Register Register Negative latch Positive latch D D Q
QM D Q G Q D D Q Q G Clk Clk Master-Slave Register Use negative clock phase to latch inputs into first latch Use positive clock to change outputs with second latch master-slave flip-flop twice as much logic
Introductory Digital Systems Laboratory 10 View pair as one basic unit L4: 6.111 Spring 2004 Latches vs. Edge-Triggered Register Regis...
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This note was uploaded on 07/21/2009 for the course EECS 6.111 taught by Professor Prof.ananthachandrakasan during the Spring '04 term at MIT.
- Spring '04