Unformatted text preview: p Flop J K S Q J
R Q K 0 1 0 1 Q+ Q 0 1 Q Q+ Q 1 0 Q 0 0 100
J K Q \Q 1 1 Eliminate the forbidden state of the SR Flip-flop Use output feedback to guarantee that R and S are never both one
Introductory Digital Systems Laboratory 14 L4: 6.111 Spring 2004 J-K Master-Slave Register Register Sample inputs while clock high Sample inputs while clock low J K S R Q Q P P S R Q Q CLK
J K Set Reset 1's Catch Toggle 100 Correct Toggle Operation Master outputs Slave outputs J
I K Q Q Clk P \P Q \Q Is there a problem with this circuit?
L4: 6.111 Spring 2004 Introductory Digital Systems Laboratory 15 Pulse Based Edge-Triggered J-K Register Register I Input X
tpLH J I K S R Q Q J I K Q Q JK Register Logic Symbol JK Register Schematic L4: 6.111 Spring 2004 Introductory Digital Systems Laboratory 16 D Flip-Flop vs. Toggle Flip-Flop Flop D Q
D Flip-Flop 1 0 1 Clk D 0 1 QN 0 1 0 1 0 1 T (Toggle) Flip-Flop T Q Clk T 0 1
L4: 6.111 Spring 2004 0
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This note was uploaded on 07/21/2009 for the course EECS 6.111 taught by Professor Prof.ananthachandrakasan during the Spring '04 term at MIT.
- Spring '04