l4_seqntl_blocks

111 spring 2004 latches vs edge triggered register

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Unformatted text preview: ter Edge triggered device sample inputs on the event edge 7474 D Q Transparent latches sample inputs as long as the clock is asserted Timing Diagram: Clk Positive edge-triggered register D Clk Q 7474 7475 D C Clk Level-sensitive latch Q Bubble here for negative edge triggered register Q7475 Behavior the same unless input changes while the clock is high Introductory Digital Systems Laboratory 11 L4: 6.111 Spring 2004 Important Timing Parameters Parameters Clock Clock: Periodic Event, causes state of memory element to change Tsu Th memory element can be updated on the: rising edge, falling edge, high level, low level Setup Time (Tsu) Minimum time before the clocking event by which the input must be stable Hold Time (Th) Minimum time after the clocking event during which the input must remain stable Propagation Delay (Tcq for an edge-triggered register and Tdq for a latch) Delay overhead of the memory element Input There is a timing There is a timing "window" around the "window" around the clocking event clocking event during which the during which the input must remain input must remain stable and stable and unchanged in order unchanged in order to be recognized to be recognized g L4: 6.111 Spring 2004 Introductory Digital Systems Laboratory 12 The J-K Flip-Flo...
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This note was uploaded on 07/21/2009 for the course EECS 6.111 taught by Professor Prof.ananthachandrakasan during the Spring '04 term at MIT.

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