l4_seqntl_blocks

69 rc 22 l4 6111 spring 2004 introductory digital

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Unformatted text preview: 1 CLout Tl,cd T > Tcq + Tlogic + Tsu L4: 6.111 Spring 2004 Introductory Digital Systems Laboratory 23 System Timing (II): Minimum Delay Delay CLout In D Q Combinational Logic D Q Clk CLK Th Th Clk IN Tsu FF1 Tcq,cd CLout Tl,cd Tcq,cd + Tlogic,cd > Thold L4: 6.111 Spring 2004 Introductory Digital Systems Laboratory 24 Shift-Register Register Typical parameters for Positive edge-triggered D Register D Tsu Th 20ns 5ns Tw 25ns Tplh 25ns 13ns Tphl 40ns 25ns Tsu 20ns Th 5ns all measurements are made from the clocking event that is, the rising edge of the clock CLK Q Shift-register IN DQ Q0 DQ Q1 100 OUT IN Q0 Q1 CLK CLK L4: 6.111 Spring 2004 Introductory Digital Systems Laboratory 25 Clocks are not perfect: Clock Skew Skew CLout In D Q Combinational Logic Wire delay D Q ClkD Clk CLK CLKD >0 T> Tcq + Tlogic + Tsu - Tcq,cd + Tlogic,cd > Thold + L4: 6.111 Spring 2004 Introductory Digital Systems Laboratory 26...
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This note was uploaded on 07/21/2009 for the course EECS 6.111 taught by Professor Prof.ananthachandrakasan during the Spring '04 term at MIT.

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