l4_seqntl_blocks

Toggle flip flop flop d q d flip flop 1 0 1 clk d 0 1

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Unformatted text preview: N-1 QN-1 0 1 0 1 Introductory Digital Systems Laboratory 17 Realizing different types of memory elements elements Characteristic Equations D: J-K: T: Q+ = D Q+ = J Q + K Q Q+ = T Q + T Q E.g., J=K=0, then Q+ = Q J=1, K=0, then Q+ = 1 J=0, K=1, then Q+ = 0 J=1, K=1, then Q+ = Q Implementing One FF in Terms of Another D J Q C K Q Q K D Q J C Q D implemented with J-K L4: 6.111 Spring 2004 J-K implemented with D 18 Introductory Digital Systems Laboratory Design Procedure Procedure Excitation Tables: What are the necessary inputs to cause a particular kind of change in state? Q Q+ 0 0 0 1 1 0 1 1 J K 0 X 1 X X 1 X 0 T 0 1 1 0 D 0 1 0 1 D Q 0 1 0 0 0 1 1 1 Implementing D FF with a J-K FF: 1) Start with K-map of Q+ = (D, Q) 2) Create K-maps for J and K with same inputs (D, Q) 3) Fill in K-maps with appropriate values for J and K to cause the same state changes as in the original K-map D Q 0 1 Q+ = D D Q 0 1 0 1 E.g., D = Q= 0, Q+ = 0 then J = 0, K = X 0 1 0 X 1 X X 1 X 0 J= D L4: 6.111 Spring 2004 K =D 19 Introductory Digital Systems Laboratory Design Procedure (cont.) (cont.) Impleme...
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  • Spring '04
  • Prof.AnanthaChandrakasan
  • Logic gate, Flip-flop, Digital Systems Laboratory, Introductory Digital Systems, Introductory Digital Systems Laboratory

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