l4_seqntl_blocks

G d q 0 q 0 then j 0 k x 0 1 0 x 1 x x 1 x

Info iconThis preview shows page 1. Sign up to view the full content.

View Full Document Right Arrow Icon
This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: nting J-K FF with a D FF: 1) K-Map of Q+ = F(J, K, Q) 2,3) Revised K-map using D's excitation table its the same! that is why design procedure with D FF is simple! JK Q 0 1 00 0 1 01 0 0 11 1 0 J 10 1 1 K Q+ = D = JQ + KQ Resulting equation is the combinational logic input to D to cause same behavior as J-K FF. Of course it is identical to the characteristic equation for a J-K FF. L4: 6.111 Spring 2004 Introductory Digital Systems Laboratory 20 System Timing Parameters Parameters In D Q Combinational Logic D Q Clk Clk Register Timing Parameters Tcq : worst case rising edge clock to q delay Tcq, cd: contamination or minimum delay from clock to q Tsu: setup time Th: hold time L4: 6.111 Spring 2004 Logic Timing Parameters Tlogic : worst case delay through the combinational logic network Tlogic,cd: contamination or minimum delay through logic network Introductory Digital Systems Laboratory 21 Delay in Digital Circuits Circuits VDD Ron Vout CL Ron Vout CL VDD (a) Low-to-high R (b) High-to-low vout C review vin tp = ln (2) W = 0.69 RC 22 L4: 6.111 Spring 2004 Introductory Digital Systems Laboratory System Timing (I): Minimum Period Period CLout In D Q Combinational Logic D Q Clk CLK Th Th Tsu Clk IN Tsu Tcq Tcq,cd Tlogic Tcq Tcq,cd Tsu2 FF...
View Full Document

This note was uploaded on 07/21/2009 for the course EECS 6.111 taught by Professor Prof.ananthachandrakasan during the Spring '04 term at MIT.

Ask a homework question - tutors are online