l4_seqntl_blocks

l4_seqntl_blocks - L4: Sequential Building Blocks Blocks...

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Unformatted text preview: L4: Sequential Building Blocks Blocks (Flip-flops, Latches and Registers) Registers) Acknowledgements: ., Materials in this lecture are courtesy of the following people and used with permission. - Randy H. Katz (University of California, Berkeley, Department of Electrical Engineering & Computer Science) - Gaetano Borriello (University of Washington, Department of Computer Science & Engineering, http://www.cs.washington.edu/370) - Rabaey, A. Chandrakasan, B. Nikolic. Digital Integrated Circuits: A Design Perspective . Prentice Hall, 2003. L4: 6.111 Spring 2004 Introductory Digital Systems Laboratory 1 Combinational Logic Review Review in0 in1 in0 Combinational Circuit in1 inN-1 inM-1 Combinational logic circuits are memoryless No feedback in combinational logic circuits Output assumes the function implemented by the logic network, assuming that the switching transients have settled Outputs can have multiple logical transitions before settling to the correct value L4: 6.111 Spring 2004 Introductory Digital Systems Laboratory 2 A Sequential System System Sequential circuits have memory (i.e., remember the past) The current state is "held" in memory and the next state is computed based the current state and the current inputs In a synchronous systems, the clock signal orchestrates the sequence of events L4: 6.111 Spring 2004 Introductory Digital Systems Laboratory 3 A Simple Example Example Adding N inputs (N-1 Adders) in0 in1 in2 inN-1 Using a sequential (serial) approach reset in DQ clk Current_Sum L4: 6.111 Spring 2004 Introductory Digital Systems Laboratory 4 Implementing State: Bi-stability stability Vo1 = Vi2 Vi2 = Vo1 Vo2 = Vi1 Point C is Metastable C V o1 Vi2 G V i2 = V o 1 Vi1 = V o2 A V i1 A V i 2 = V o1 C V o2 Points A and B are stable (represent 0 & 1) B V i 1 = V o2 L4: 6.111 Spring 2004 Introductory Digital Systems Laboratory B G V i1 = V o2 5 NOR-based Set-Reset (SR) Flipflop Flipflop S R S Q Q S 0 Q 1 0 1 R 0 0 1 1 Q Q 1 0 0 Q Q 0 1 0 QQ 01 SR = 0 1 SR = 0 1 SR = 1 0 SR = 00, 01 SR = 1 0 SR = 00, 10 QQ 10 SR = 11 SR = 1 1 QQ 00 SR = 1 1 R Reset Q Forbidden State SR = 0 0 SR = 0 0 Hold Set Reset Set R S Q Q ?? Flip-flop refers to a bi-stable element (edge-triggered registers are also called flip-flops) this circuit is not clocked and outputs change "asynchronously" with the inputs L4: 6.111 Spring 2004 Introductory Digital Systems Laboratory 6 Making a Clocked Memory Element: Element: Positive D-Latch Latch D CLK R S Q hold sample hold sample hold D G Q R and S clock clk A Positive D-Latch: Passes input D to output Q when CLK is high and holds state when clock is low (i.e., ignores input D) A Latch is level-sensitive: invert clock for a negative latch L4: 6.111 Spring 2004 Introductory Digital Systems Laboratory 7 Multiplexor Based Positive & Negative Latch Latch 2:1 multiplexor in0 in1 0 out 1 D SEL 0 Q 1 D 1 Q 0 Positive Latch Negative Latch Out = sel * in1 + sel * in0 CLK CLK clk clk "data" "load" "remember" "stored value" L4: 6.111 Spring 2004 Introductory Digital Systems Laboratory 8 Building an Edge-Triggered Register Register Negative latch Positive latch D D Q QM D Q G Q D D Q Q G Clk Clk Master-Slave Register Use negative clock phase to latch inputs into first latch Use positive clock to change outputs with second latch master-slave flip-flop twice as much logic Introductory Digital Systems Laboratory 10 View pair as one basic unit L4: 6.111 Spring 2004 Latches vs. Edge-Triggered Register Register Edge triggered device sample inputs on the event edge 7474 D Q Transparent latches sample inputs as long as the clock is asserted Timing Diagram: Clk Positive edge-triggered register D Clk Q 7474 7475 D C Clk Level-sensitive latch Q Bubble here for negative edge triggered register Q7475 Behavior the same unless input changes while the clock is high Introductory Digital Systems Laboratory 11 L4: 6.111 Spring 2004 Important Timing Parameters Parameters Clock Clock: Periodic Event, causes state of memory element to change Tsu Th memory element can be updated on the: rising edge, falling edge, high level, low level Setup Time (Tsu) Minimum time before the clocking event by which the input must be stable Hold Time (Th) Minimum time after the clocking event during which the input must remain stable Propagation Delay (Tcq for an edge-triggered register and Tdq for a latch) Delay overhead of the memory element Input There is a timing There is a timing "window" around the "window" around the clocking event clocking event during which the during which the input must remain input must remain stable and stable and unchanged in order unchanged in order to be recognized to be recognized g L4: 6.111 Spring 2004 Introductory Digital Systems Laboratory 12 The J-K Flip-Flop Flop J K S Q J R Q K 0 1 0 1 Q+ Q 0 1 Q Q+ Q 1 0 Q 0 0 100 J K Q \Q 1 1 Eliminate the forbidden state of the SR Flip-flop Use output feedback to guarantee that R and S are never both one Introductory Digital Systems Laboratory 14 L4: 6.111 Spring 2004 J-K Master-Slave Register Register Sample inputs while clock high Sample inputs while clock low J K S R Q Q P P S R Q Q CLK J K Set Reset 1's Catch Toggle 100 Correct Toggle Operation Master outputs Slave outputs J I K Q Q Clk P \P Q \Q Is there a problem with this circuit? L4: 6.111 Spring 2004 Introductory Digital Systems Laboratory 15 Pulse Based Edge-Triggered J-K Register Register I Input X Input I Output Schematic Output X tpLH J I K S R Q Q J I K Q Q JK Register Logic Symbol JK Register Schematic L4: 6.111 Spring 2004 Introductory Digital Systems Laboratory 16 D Flip-Flop vs. Toggle Flip-Flop Flop D Q D Flip-Flop 1 0 1 Clk D 0 1 QN 0 1 0 1 0 1 T (Toggle) Flip-Flop T Q Clk T 0 1 L4: 6.111 Spring 2004 0 QN Q N-1 QN-1 0 1 0 1 Introductory Digital Systems Laboratory 17 Realizing different types of memory elements elements Characteristic Equations D: J-K: T: Q+ = D Q+ = J Q + K Q Q+ = T Q + T Q E.g., J=K=0, then Q+ = Q J=1, K=0, then Q+ = 1 J=0, K=1, then Q+ = 0 J=1, K=1, then Q+ = Q Implementing One FF in Terms of Another D J Q C K Q Q K D Q J C Q D implemented with J-K L4: 6.111 Spring 2004 J-K implemented with D 18 Introductory Digital Systems Laboratory Design Procedure Procedure Excitation Tables: What are the necessary inputs to cause a particular kind of change in state? Q Q+ 0 0 0 1 1 0 1 1 J K 0 X 1 X X 1 X 0 T 0 1 1 0 D 0 1 0 1 D Q 0 1 0 0 0 1 1 1 Implementing D FF with a J-K FF: 1) Start with K-map of Q+ = (D, Q) 2) Create K-maps for J and K with same inputs (D, Q) 3) Fill in K-maps with appropriate values for J and K to cause the same state changes as in the original K-map D Q 0 1 Q+ = D D Q 0 1 0 1 E.g., D = Q= 0, Q+ = 0 then J = 0, K = X 0 1 0 X 1 X X 1 X 0 J= D L4: 6.111 Spring 2004 K =D 19 Introductory Digital Systems Laboratory Design Procedure (cont.) (cont.) Implementing J-K FF with a D FF: 1) K-Map of Q+ = F(J, K, Q) 2,3) Revised K-map using D's excitation table its the same! that is why design procedure with D FF is simple! JK Q 0 1 00 0 1 01 0 0 11 1 0 J 10 1 1 K Q+ = D = JQ + KQ Resulting equation is the combinational logic input to D to cause same behavior as J-K FF. Of course it is identical to the characteristic equation for a J-K FF. L4: 6.111 Spring 2004 Introductory Digital Systems Laboratory 20 System Timing Parameters Parameters In D Q Combinational Logic D Q Clk Clk Register Timing Parameters Tcq : worst case rising edge clock to q delay Tcq, cd: contamination or minimum delay from clock to q Tsu: setup time Th: hold time L4: 6.111 Spring 2004 Logic Timing Parameters Tlogic : worst case delay through the combinational logic network Tlogic,cd: contamination or minimum delay through logic network Introductory Digital Systems Laboratory 21 Delay in Digital Circuits Circuits VDD Ron Vout CL Ron Vout CL VDD (a) Low-to-high R (b) High-to-low vout C review vin tp = ln (2) W = 0.69 RC 22 L4: 6.111 Spring 2004 Introductory Digital Systems Laboratory System Timing (I): Minimum Period Period CLout In D Q Combinational Logic D Q Clk CLK Th Th Tsu Clk IN Tsu Tcq Tcq,cd Tlogic Tcq Tcq,cd Tsu2 FF1 CLout Tl,cd T > Tcq + Tlogic + Tsu L4: 6.111 Spring 2004 Introductory Digital Systems Laboratory 23 System Timing (II): Minimum Delay Delay CLout In D Q Combinational Logic D Q Clk CLK Th Th Clk IN Tsu FF1 Tcq,cd CLout Tl,cd Tcq,cd + Tlogic,cd > Thold L4: 6.111 Spring 2004 Introductory Digital Systems Laboratory 24 Shift-Register Register Typical parameters for Positive edge-triggered D Register D Tsu Th 20ns 5ns Tw 25ns Tplh 25ns 13ns Tphl 40ns 25ns Tsu 20ns Th 5ns all measurements are made from the clocking event that is, the rising edge of the clock CLK Q Shift-register IN DQ Q0 DQ Q1 100 OUT IN Q0 Q1 CLK CLK L4: 6.111 Spring 2004 Introductory Digital Systems Laboratory 25 Clocks are not perfect: Clock Skew Skew CLout In D Q Combinational Logic Wire delay D Q ClkD Clk CLK CLKD >0 T> Tcq + Tlogic + Tsu - Tcq,cd + Tlogic,cd > Thold + L4: 6.111 Spring 2004 Introductory Digital Systems Laboratory 26 ...
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This note was uploaded on 07/21/2009 for the course EECS 6.111 taught by Professor Prof.ananthachandrakasan during the Spring '04 term at MIT.

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