l5_seqntlverilog

l5_seqntlverilog - L5: Simple Sequential Circuits and...

Info iconThis preview shows page 1. Sign up to view the full content.

View Full Document Right Arrow Icon
This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: L5: Simple Sequential Circuits and Verilog Courtesy of Rex Min. Used with permission. L5: 6.111 Spring 2004 Introductory Digital Systems Laboratory 1 Key Points from L4 (Sequential Blocks) Classification: Latch: level sensitive (positive latch passes input to output on high phase, hold value on low phase) Register: edge-triggered (positive register samples input on rising edge) Flip-Flop: any element that has two stable states. Quite often Flip-flop also used denote an (edge-triggered) register Positive Latch D D Q Q D D Q Q Positive Register Clk Clk Latches are used to build Registers (using the Master-Slave Configuration), but are almost NEVER used by itself in a standard digital design flow. Quite often, latches are inserted in the design by mistake (e.g., an error in your Verilog code). Make sure you understand the difference between the two. Several types of memory elements (SR, JK, T, D). We will most commonly use the D-Register, though you should understand how the different types are built and their functionality. L5: 6.111 Spring 2004 Introductory Digital Systems Laboratory 2 Key Points from L4 : System Timing CLout In D Q Combinational Logic D Q Clk CLK Th Th Tsu Clk IN Tsu Tcq Tcq,cd Tlogic Tsu Tcq Tcq,cd FF1 CLout Tl,cd T > Tcq + Tlogic + Tsu L5: 6.111 Spring 2004 Tcq,cd + Tlogic,cd > Thold 3 Introductory Digital Systems Laboratory The Sequential always Block Edge-triggered circuits are described using a sequential always block Combinational module combinational(a, b, sel, out); input a, b; input sel; output out; reg out; always @ (a or b or sel) begin if (sel) out = a; else out = b; end endmodule Sequential module sequential(a, b, sel, clk, out); input a, b; input sel, clk; output out; reg out; always @ (posedge clk) begin if (sel) out <= a; else out <= b; end endmodule a b 1 out 0 sel a b 1 D Q 0 sel clk 4 out L5: 6.111 Spring 2004 Introductory Digital Systems Laboratory Importance of the Sensitivity List The use of posedge and negedge makes an always block sequential (edge-triggered) Unlike a combinational always block, the sensitivity list does determine behavior for synthesis! D Flip-flop with synchronous clear module dff_sync_clear(d, clearb, clock, q); input d, clearb, clock; output q; reg q; always @ (posedge clock) begin if (!clearb) q <= 1'b0; else q <= d; end endmodule D Flip-flop with asynchronous clear module dff_async_clear(d, clearb, clock, q); input d, clearb, clock; output q; reg q; always @ (negedge clearb or posedge clock) begin if (!clearb) q <= 1'b0; else q <= d; end endmodule always block entered only at each positive clock edge always block entered immediately when (active-low) clearb is asserted Note: The following is incorrect syntax: always @ (clear or negedge clock) If one signal in the sensitivity list uses posedge/negedge, then all signals must. Assign any signal or variable from only one always block, Be wary of race conditions: always blocks execute in parallel L5: 6.111 Spring 2004 Introductory Digital Systems Laboratory 5 Simulation DFF with Synchronous Clear tc-q Clear on Clock Edge DFF with Asynchronous Clear Clear happens on falling edge of clearb L5: 6.111 Spring 2004 Introductory Digital Systems Laboratory 6 Blocking vs. Nonblocking Assignments Verilog supports two types of assignments within always blocks, with subtly different behaviors. Blocking assignment: evaluation and assignment are immediate always @ (a or b or c) begin 1. Evaluate a | b, assign result to x x = a | b; 2. Evaluate a^b^c, assign result to y y = a ^ b ^ c; z = b & ~c; 3. Evaluate b&(~c), assign result to z end Nonblocking assignment: all assignments deferred until all right-hand sides have been evaluated (end of simulation timestep) always begin x <= y <= z <= end @ (a or b or c) a | b; a ^ b ^ c; b & ~c; 1. Evaluate a | b but defer assignment of x 2. Evaluate a^b^c but defer assignment of y 3. Evaluate b&(~c) but defer assignment of z 4. Assign x, y, and z with their new values Sometimes, as above, both produce the same result. Sometimes, not! L5: 6.111 Spring 2004 Introductory Digital Systems Laboratory 7 Assignment Styles for Sequential Logic Flip-Flop Based Digital Delay Line in clk D Q q1 D Q q2 D Q out Will nonblocking and blocking assignments both produce the desired result? module nonblocking(in, clk, out); input in, clk; output out; reg q1, q2, out; always @ (posedge clk) begin q1 <= in; q2 <= q1; out <= q2; end endmodule module blocking(in, clk, out); input in, clk; output out; reg q1, q2, out; always @ (posedge clk) begin q1 = in; q2 = q1; out = q2; end endmodule L5: 6.111 Spring 2004 Introductory Digital Systems Laboratory 8 Use Nonblocking for Sequential Logic always @ (posedge clk) begin q1 <= in; q2 <= q1; out <= q2; end "At each rising clock edge, q1, q2, and out simultaneously receive the old values of in, q1, and q2." always @ (posedge clk) begin q1 = in; q2 = q1; out = q2; end "At each rising clock edge, q1 = in. After that, q2 = q1 = in. After that, out = q2 = q1 = in. Therefore out = in." q1 q2 D Q q1 in clk D Q D Q q2 D Q out clk in out Blocking assignments do not reflect the intrinsic behavior of multi-stage sequential logic Guideline: use nonblocking assignments for sequential always blocks L5: 6.111 Spring 2004 Introductory Digital Systems Laboratory 9 Simulation Non-blocking Simulation Blocking Simulation L5: 6.111 Spring 2004 Introductory Digital Systems Laboratory 10 Use Blocking for Combinational Logic Blocking Behavior (Given) Initial Condition a changes; always block triggered abc xy 110 010 010 010 11 11 01 00 a b c x y module blocking(a,b,c,x,y); input a,b,c; output x,y; reg x,y; always @ (a or b or c) begin x = a & b; y = x | c; end endmodule x = a & b; y = x | c; Nonblocking Behavior (Given) Initial Condition a changes; always block triggered abc xy 110 010 010 010 010 11 11 11 11 01 Deferred module nonblocking(a,b,c,x,y); input a,b,c; output x,y; reg x,y; always @ (a or b or c) begin x <= a & b; y <= x | c; end endmodule x <= a & b; y <= x | c; Assignment completion x<=0 x<=0, y<=1 Nonblocking and blocking assignments will synthesize correctly. Will both styles simulate correctly? Nonblocking assignments do not reflect the intrinsic behavior of multi-stage combinational logic While nonblocking assignments can be hacked to simulate correctly (expand the sensitivity list), it's not elegant Guideline: use blocking assignments for combinational always blocks L5: 6.111 Spring 2004 Introductory Digital Systems Laboratory 11 The Asynchronous Ripple Counter A simple counter architecture uses only registers (e.g., 74HC393 uses T-register and negative edge-clocking) Toggle rate fastest for the LSB ...but ripple architecture leads to large skew between outputs D Q Q Count [3:0] Count[0] Count[1] Count[2] Count[3] D Q Q D Q Q D Q Q Clock D register set up to always toggle: i.e., T Register with T=1 Skew Count [3] Count [2] Count [1] Count [0] Clock L5: 6.111 Spring 2004 Introductory Digital Systems Laboratory 12 The Ripple Counter in Verilog Single D Register with Asynchronous Clear: module dreg_async_reset (clk, clear, d, q, qbar); input d, clk, clear; output q, qbar; reg q; always @ (posedge clk or negedge clear) begin if (!clear) q <= 1'b0; else q <= d; end assign qbar = ~q; endmodule Count [3:0] Count[0] Count[1] Count[2] Count[3] D Q Q D Q Q Countbar[0] D Q Q Countbar[1] D Q Q Countbar[3] Countbar[2] Clock Structural Description of Four-bit Ripple Counter: module ripple_counter (clk, count, clear); input clk, clear; output [3:0] count; wire [3:0] count, countbar; dreg_async_reset bit0(.clk(clk), .clear(clear), .d(countbar[0]), .q(count[0]), .qbar(countbar[0])); dreg_async_reset bit1(.clk(countbar[0]), .clear(clear), .d(countbar[1]), .q(count[1]), .qbar(countbar[1])); dreg_async_reset bit2(.clk(countbar[1]), .clear(clear), .d(countbar[2]), .q(count[2]), .qbar(countbar[2])); dreg_async_reset bit3(.clk(countbar[2]), .clear(clear), .d(countbar[3]), .q(count[3]), .qbar(countbar[3])); endmodule L5: 6.111 Spring 2004 Introductory Digital Systems Laboratory 13 Simulation of Ripple Effect L5: 6.111 Spring 2004 Introductory Digital Systems Laboratory 14 Logic for a Synchronous Counter Count (C) will retained by a D Register Next value of counter (N) computed by combinational logic C3 0 0 0 0 1 1 1 1 C2 0 0 1 1 0 0 1 1 C1 0 1 0 1 0 1 0 1 N3 0 0 0 1 1 1 1 0 N2 0 1 1 0 0 1 1 0 N1 1 0 1 0 1 0 1 0 N1 C3 1 1 0 1 0 1 0 N2 C3 0 1 0 1 0 0 1 C1 0 C1 1 C3 0 1 1 0 1 1 C2 N3 0 C2 C1 0 C2 C1 C2 D Q D Q C3 N1 := C1 N2 := C1 C2 + C1 C2 := C1 xor C2 N3 := C1 C2 C3 + C1 C3 + C2 C3 := C1 C2 C3 + (C1 + C2 ) C3 := (C1 C2) xor C3 CLK D Q From [Katz93], See Chapter 7 for different counters L5: 6.111 Spring 2004 Introductory Digital Systems Laboratory 15 The 74163 Catalog Counter Synchronous Load and Clear Inputs Positive Edge Triggered FFs Parallel Load Data from D, C, B, A P, T Enable Inputs: both must be asserted to enable counting Ripple Carry Output (RCO): asserted when counter value is 1111 (conditioned by T); used for cascading counters 9 1 7 P 10 T 163 15 2 CLK RCO 6 5 4 3 D C B A LOAD CLR QD QC QB QA 11 12 13 14 Synchronous CLR and LOAD If CLRb = 0 then Q <= 0 Else if LOADb=0 then Q <= D Else if P * T = 1 then Q <= Q + 1 Else Q <= Q 74163 Synchronous 4-Bit Upcounter L5: 6.111 Spring 2004 Introductory Digital Systems Laboratory 16 Verilog Code for `163 Behavioral description of the `163 counter: module counter(LDbar, CLRbar, P, T, CLK, D, count, RCO); input LDbar, CLRbar, P, T, CLK; input [3:0] D; output [3:0] count; output RCO; reg [3:0] Q; always @ (posedge CLK) begin if (!CLRbar) Q <= 4'b0000; else if (!LDbar) Q <= D; else if (P && T) Q <= Q + 1; end 7 P 10 T 163 15 2 CLK RCO 6 5 4 3 9 1 D C B A LOAD CLR QD QC QB QA 11 12 13 14 priority logic for control signals assign count = Q; assign RCO = Q[3] & Q[2] & Q[1] & Q[0] & T; endmodule RCO gated by T input L5: 6.111 Spring 2004 Introductory Digital Systems Laboratory 19 Simulation Notice the glitches on RCO! L5: 6.111 Spring 2004 Introductory Digital Systems Laboratory 20 Output Transitions Any time multiple bits change, the counter output needs time to settle. Even though all flip-flops share the same clock, individual bits will change at different times. Clock skew, propagation time variations Can cause glitches in combinational logic driven by the counter The RCO can also have a glitch. L5: 6.111 Spring 2004 Introductory Digital Systems Laboratory 21 Cascading the 74163: Will this Work? VDD T P bits 0-3 QA QB QC QD T P bits 4-7 QA QB QC QD bits 8-11 T P QA QB QC QD `163 CL LD RCO `163 CL LD RCO `163 CL LD RCO DA DB DC DD DA DB DC DD DA DB DC DD VDD CLK `163 is enabled only if P and T are high When first counter reaches Q = 4'b1111, its RCO goes high for one cycle When RCO goes high, next counter is enabled (P T = 1) So far, so good...then what's wrong? L5: 6.111 Spring 2004 Introductory Digital Systems Laboratory 22 Incorrect Cascade for 74163 Everything is fine up to 8'b11101111: VDD T P 1 1 1 1 QA QB QC QD T 0 1 1 1 1 P QA QB QC QD T 0 0 0 0 0 QA QB QC QD P `163 CL LD RCO `163 CL LD RCO `163 CL LD RCO DA DB DC DD DA DB DC DD DA DB DC DD VDD CLK Problem at 8'b11110000: one of the RCOs is now stuck high for 16 cycles! VDD T P 0 0 0 0 QA QB QC QD T 1 1 1 1 0 P QA QB QC QD 0 0 0 0 1 P T QA QB QC QD `163 CL LD RCO `163 CL LD RCO `163 CL LD RCO DA DB DC DD DA DB DC DD DA DB DC DD VDD CLK Introductory Digital Systems Laboratory 23 L5: 6.111 Spring 2004 Correct Cascade for 74163 Master enable P T CL LD QA QB QC QD RCO DA DB DC DD T CL LD P QA QB QC QD RCO DA DB DC DD P input takes the master enable T input takes the ripple carry assign RCO = Q[3] & Q[2] & Q[1] & Q[0] & T; L5: 6.111 Spring 2004 Introductory Digital Systems Laboratory 24 Summary Use blocking assignments for combinational always blocks Use non-blocking assignments for sequential always blocks Synchronous design methodology usually used in digital circuits Single global clocks to all sequential elements Sequential elements almost always of edge-triggered flavor (design with latches can be tricky) Today we saw simple examples of sequential circuits (counters) L5: 6.111 Spring 2004 Introductory Digital Systems Laboratory 25 ...
View Full Document

This note was uploaded on 07/21/2009 for the course EECS 6.111 taught by Professor Prof.ananthachandrakasan during the Spring '04 term at MIT.

Ask a homework question - tutors are online