l6_fsm_toCMS_080904

l6_fsm_toCMS_080904 - L6: FSMs and Synchronization Courtesy...

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L6: 6.111 Spring 2004 1 Introductory Digital Systems Laboratory L6: L6: FSMs FSMs and Synchronization and Synchronization C ourtesy of Rex Min . Used with permission.
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L6: 6.111 Spring 2004 2 Introductory Digital Systems Laboratory Asynchronous Inputs in Sequential Systems Asynchronous Inputs in Sequential Systems What about external signals? Can’t guarantee setup and hold times will be met! Sequential System Clock When an asynchronous signal causes a setup/hold violation. .. I III Clock Q D II ? Output is metastable for an indeterminate amount of time. Transition is missed on first clock cycle, but caught on next clock cycle. Transition is caught on first clock cycle. Q: Which cases are problematic?
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L6: 6.111 Spring 2004 3 Introductory Digital Systems Laboratory Asynchronous Inputs in Sequential Systems Asynchronous Inputs in Sequential Systems All of them can be, if more than one happens simultaneously within the same circuit. Idea: ensure that external signals directly feed exactly one flip-flop D Q D Q Q0 Clock Clock Q1 Async Input Clocked Synchronous System DQ Sequential System Clock This prevents the possibility of I and II occurring in different places in the circuit, but what about metastability?
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L6: 6.111 Spring 2004 4 Introductory Digital Systems Laboratory Handling Handling Metastability Metastability ¡ Preventing metastability turns out to be an impossible problem ¡ High gain of digital devices makes it likely that metastable conditions will resolve themselves quickly ¡ Solution to metastability: allow time for signals to stabilize Likeley to be metastable right after sampling Extremely unlikely to be metastable for >2 clock cycle Very unlikely to be metastable for >1 clock cycle DQ Complicated Sequential Logic System Clock How many registers are necessary? ¡ Depends on many design parameters(clock speed, device speeds, …) ¡ In 6.111, one or maybe two synchronization registers is sufficient
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L6: 6.111 Spring 2004 5 Introductory Digital Systems Laboratory Finite State Machines Finite State Machines ¡ Finite State Machines (FSMs) are a useful abstraction for sequential circuits with centralized “states” of operation ¡ At each clock edge, combinational logic computes outputs and next state as a function of inputs and present state Combinational Logic Flip- Flops Q D inputs + present state outputs + next state n n CLK
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L6: 6.111 Spring 2004 6 Introductory Digital Systems Laboratory Two Types of Two Types of FSMs FSMs Moore and Mealy FSMs are distinguished by their output generation inputs x 0 ... x n Moore FSM: Comb. Logic CLK n Flip- Flops Comb. Logic D Q present state S n next state S + outputs y k = f k ( S ) Mealy FSM: S Comb. Logic CLK Flip- Flops Comb. Logic D Q n S + n direct combinational path! outputs y k = f k ( S, x 0 ...x n ) inputs x 0 ... x n
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L6: 6.111 Spring 2004 7 Introductory Digital Systems Laboratory Design Example: Level Design Example: Level - - to to - - Pulse Pulse ¡ A level-to-pulse converter produces a single-cycle pulse each time its input goes high.
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This note was uploaded on 07/21/2009 for the course EECS 6.111 taught by Professor Prof.ananthachandrakasan during the Spring '04 term at MIT.

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l6_fsm_toCMS_080904 - L6: FSMs and Synchronization Courtesy...

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