l9_analog

l9_analog - L9: Analog Building Blocks (OpAmps, A/D, D/A)...

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Unformatted text preview: L9: Analog Building Blocks (OpAmps, A/D, D/A) Courtesy of Dave Wentzloff. Used with permission. L9: 6.111 Spring 2004 Introductory Digital Systems Laboratory 1 Introduction to Operational Amplifiers DC Model Rin vid a vid Rout Typically very high input resistance ~ 300K High DC gain (~105) vout Output resistance ~75 Vout LM741 Pinout +10 to +15V a ( f ) Vin a(f) 10 5 -20dB/ decade f 2 -10 to -15V 10Hz (Reprinted with permission of National Semiconductor Corporation. Used with permission.) L9: 6.111 Spring 2004 Introductory Digital Systems Laboratory The Inside of a 741 OpAmp Differential Input Stage Current Source Additional for biasing Gain Stage Output Stage Output devices provides large drive current Bipolar version has small input Bias current MOS OpAmps have ~ 0 input current Gain is Sensitive to Operating Condition (e.g., Device, Temperature, Power supply voltage, etc.) (Reprinted with permission of National Semiconductor Corporation. Used with permission.) L9: 6.111 Spring 2004 Introductory Digital Systems Laboratory 3 Simple Model for an OpAmp i+ ~ 0 + + vid i- ~ 0 Reasonable approximation VCC vout + vout -100 V VCC = 10V = 100 V -VCC = -10V vid -VCC Linear Mode Negative Saturation + - Positive Saturation vid + + - avid vout vid + - + - -VCC vout - + vid + - + - +VCC vout - + If -VCC < vout < VCC vid < - vid > Small input range for "Open" loop Configuration L9: 6.111 Spring 2004 Introductory Digital Systems Laboratory 4 The Power of (Negative) Feedback R1 vin + - + R2 vout vin + - R1 - R2 vid vin R1 + + avid vout - + vin R1 vid vout R2 vout vin vid 0 R2 a vid vout a vout 1 a R1 a R2 1 R2 1 a R1 R2 R2 if R1 a 1 Overall (closed loop) gain does not depend of open loop gain Trade gain for robustness Easier analysis approach: "virtual short circuit approach" v+ = v- = 0 if OpAmp is linear L9: 6.111 Spring 2004 Introductory Digital Systems Laboratory 5 Basic OpAmp Circuits Voltage Follower (buffer) Non-inverting vin + - vin vout vout R2 R1 vout R1 R2 R1 vout vin1 vin 2 R1 R1 R2 R1 vin R2 vin Differential Input Integrator vout R2 vin R C vout t vout L9: 6.111 Spring 2004 vin 2 vin1 vout 1 RC vin dt 6 Introductory Digital Systems Laboratory Use With Open Loop Analog Comparator: Is V+ > V- ? The Output is a DIGITAL signal LM311 is a single supply comparator L9: 6.111 Spring 2004 Introductory Digital Systems Laboratory 7 Data Conversion: Quantization Noise A/D Conversion Binary Output D/A Conversion Analog Output 3Vref 4 Vref 2 Vref 4 11 10 01 00 0 Vref 4 Vref 2 3Vref 4 Vref Analog Input 0 00 01 10 11 Binary code digital code vin A/D D/A Quantization noise vnoise LSB Quantization noise exists even with ideal A/D and D/A converters Vref 4 Vref 2 3Vref 4 Vref v in 8 L9: 6.111 Spring 2004 Introductory Digital Systems Laboratory Non-idealities in Data Conversion Offset a constant voltage offset that appears at the output when the digital input is 0 Gain error deviation of slope from ideal value of 1 Analog Analog Offset error Ideal Gain error Ideal Binary code Binary code Integral Nonlinearity maximum deviation from Differential nonlinearity the largest increment the ideal analog output voltage in analog output for a 1-bit change Integral nonlinearity Analog Ideal Analog Ideal Nonmonoticity Binary code L9: 6.111 Spring 2004 Binary code Introductory Digital Systems Laboratory 9 R-2R Ladder DAC Architecture -1 Note that the driving point impedance (resistance) is the same for each cell. R-2R Ladder achieves large current division ratios with only two resistor values L9: 6.111 Spring 2004 Introductory Digital Systems Laboratory 10 DAC (AD 558) Specs - Used in Lab 3 8-bit DAC Single Supply Operation: 5V to 15V Integrates required references (bandgap voltage reference) Uses a R-2R resistor ladder Settling time 1 s Programmable output range from 0V to 2.56V or 0V to 10V Simple Latch based interface (Courtesy of Analog Devices. Used with permission.) L9: 6.111 Spring 2004 Introductory Digital Systems Laboratory 11 Chip Architecture and Interface D[7:0] LATCH CE CS Outputs are noisy when input bits settles, so it is best to have inputs stable before latching the input data L9: 6.111 Spring 2004 (Courtesy of Analog Devices. Used with permission.) Introductory Digital Systems Laboratory 12 Setting the Voltage Range Very similar to a non-inverting amp Strap output for different voltage ranges Convert data to Offset binary L9: 6.111 Spring 2004 (Courtesy of Analog Devices. Used with permission.) Introductory Digital Systems Laboratory 13 Another Approach: Binary-Weighted DAC R Switch binary-weighted currents b3 I I 2 b2 I 4 b1 1 2 I 8 b0 1 4 + 1 8 vout MSB to LSB current ratio is 2N vout IR b3 b2 b1 b0 AD9768 Analog Devices AD9768 uses two banks of ratioed currents Additional current division performed by 750 resistor between the two banks Reference current source L9: 6.111 Spring 2004 (Courtesy of Analog Devices. Used with permission.) Introductory Digital Systems Laboratory 14 Glitching and Thermometer D/A Glitching is caused when switching times in a D/A are not synchronized Example: Output changes from 011 to 100 MSB switch is delayed Filtering reduces glitch but increases the D/A settling time One solution is a thermometer code D/A requires 2N 1 switches but no ratioed currents Binary 0 0 1 1 0 1 0 1 Thermometer 0 0 0 1 0 0 1 1 0 1 1 1 R vout vout 011 100 I T0 I T1 I T2 t L9: 6.111 Spring 2004 vout IR T0 T1 T2 15 Introductory Digital Systems Laboratory Successive-Approximation A/D D/A converters are typically compact and easier to design. Why not A/D convert using a D/A converter and a comparator? D to A generates analog voltage which is compared to the input voltage If D to A voltage > input voltage then set that bit; otherwise, reset that bit This type of A to D takes a fixed amount of time proportional to the bit length Vin code D/A C Comparator out L9: 6.111 Spring 2004 Example: 3-bit A/D conversion, 2 LSB < Vin < 3 LSB Introductory Digital Systems Laboratory 16 Successive-Approximation A/D Data D/A Converter vin Sample/ Hold + Control Go Successive Approximation Generator Done N Serial conversion takes a time equal to N(tD/A + tcomp) L9: 6.111 Spring 2004 Introductory Digital Systems Laboratory 17 Successive-Approximation A/D (AD670) Used in Lab 3 Unipolar (BPO =0) ~10s conversion time Bipolar (BPO =1) (Courtesy of Analog Devices. Used with permission.) L9: 6.111 Spring 2004 Introductory Digital Systems Laboratory 18 Single Write, Single Read Operation (see data sheet for other modes) R/W CE, CS Status Data Valid tw Write Read tDC tc tTD tDT Data Valid tw (write/start pulse width) = 300ns (min) tDC (delay to start conversion) = 700ns (max) tc (conversion time) = 10 s (max) tTD (Bus Access Time) = 250 (max) tDT (Output Float Delay) = 150 (max) Control bits CE and CS can be wired to ground if A/D is the only chip driving the bus Tie the CE and CS pins together for lab3 and hardwire BPO and Format L9: 6.111 Spring 2004 Introductory Digital Systems Laboratory 19 Simple A/D Interface FSM clk reset sample FSM cs_b r_w_b status CS CE R/W AD670 STATUS Data[7:0] dataavail Q D Status should be synchronized: why? Courtesy of James Oey and Cemal Akcaba L9: 6.111 Spring 2004 Introductory Digital Systems Laboratory 20 Example A/D Verilog Interface module AD670 (clk, reset, sample, dataavail, r_wbar, cs_bar, status, state); // System Clk input clk; // Global Reset signal, assume it is synchronized input reset; // User Interface input sample; output dataavail; // A-D Interface input status; reg status_d1, status_d2; output r_wbar, cs_bar; output [3:0] state; // internal state reg [3:0] state; reg [3:0] nextstate; reg r_wbar_int, r_wbar; reg cs_bar_int, cs_bar; reg dataavail; // State declarations. parameter IDLE = 0; parameter CONV0 = 1; parameter CONV1 = 2; parameter CONV2 = 3; parameter WAITSTATUSHIGH = 4; parameter WAITSTATUSLOW = 5; parameter READDELAY0 = 6; parameter READDELAY1 = 7; parameter READCYCLE = 8; always @ (posedge clk or negedge reset) begin if (!reset) state <=IDLE; else state <=nextstate; status_d1 <= status; status_d2 <= status_d1; r_wbar <= r_wbar_int; cs_bar <=cs_bar_int; end 1/5 Introductory Digital Systems Laboratory 2/5 21 L9: 6.111 Spring 2004 Example A/D Verilog Interface (cont.) always @ (state or status_d2 or sample) begin // defaults r_wbar_int = 1; cs_bar_int = 1; dataavail = 0; case (state) IDLE: begin if(sample) nextstate = CONV0; else nextstate = IDLE; end CONV0: begin r_wbar_int = 0; cs_bar_int = 0; nextstate = CONV1; end CONV1: begin r_wbar_int = 0; cs_bar_int = 0; nextstate = CONV2; end CONV2: begin r_wbar_int = 0; cs_bar_int = 0; nextstate = WAITSTATUSHIGH; end WAITSTATUSHIGH: begin cs_bar_int = 0; if (status_d2) nextstate = WAITSTATUSLOW; else nextstate = WAITSTATUSHIGH; end WAITSTATUSLOW: begin cs_bar_int = 0; if (!status_d2) nextstate = READDELAY0; else nextstate = WAITSTATUSLOW; end 3/5 L9: 6.111 Spring 2004 Introductory Digital Systems Laboratory 4/5 22 Example A/D Verilog Interface(cont.) READDELAY0: begin cs_bar_int = 0; nextstate = READDELAY1; end READDELAY1: begin cs_bar_int = 0; nextstate = READCYCLE; end READCYCLE: begin cs_bar_int = 0; dataavail = 1; nextstate = IDLE; end default: nextstate = IDLE; endcase // case(state) end // always @ (state or status_d2 or sample) endmodule // adcInterface 5/5 L9: 6.111 Spring 2004 Introductory Digital Systems Laboratory 23 Simulation On reset, present state goes to 0 r_w_b must stay low for at least 3 cycles (@ 100ns period) Don't need 3 cycles if you use the 1.8432MHz clock Enable read flip-flop Status is synchronized two register delays Wait for ~10 s for status to go low Sample pulse initiates Notice a one cycle delay since A/D data conversion control signal delayed through a register L9: 6.111 Spring 2004 Introductory Digital Systems Laboratory 24 Flash A/D Converter Vref vin Brute-force A/D conversion C The rmom eter to binary R Simultaneously compare the analog value with every possible reference value b0 b1 R C R Fastest method of A/D conversion Size scales exponentially with precision (requires 2N comparators) C Comparators R Another example of OpAmp in open loop L9: 6.111 Spring 2004 Introductory Digital Systems Laboratory 25 AD 775 Flash Data Converter (Courtesy of Analog Devices. Used with permission.) L9: 6.111 Spring 2004 Introductory Digital Systems Laboratory 26 High Performance Converters: Use Pipelining and Parallelism! Pipelining (used in video rate, RF basestations, etc.) 1-bit Amplifier 2 Sample/ Hold A/D Converter 1-bit Amplifier 2 Sample/ Hold A/D Converter D/A Converter D/A Converter ... Parallelism (use many slower A/D's in parallel to build very high speed A/D converters) [ISSCC 2003], Poulton et. al. 20Gsample/sec, 8-bit ADC from Agilent Labs L9: 6.111 Spring 2004 Introductory Digital Systems Laboratory 27 Summary of Analog Blocks Analog blocks are integral components of any system. Need data converters (analog to digital and digital to analog), analog processing (OpAmps circuits, switched capacitors filters, etc.), power converters (e.g., DC-DC conversion), etc. We looked at example interfaces for A/D and D/A converters Make sure you register critical signals (enables, R/W, etc.) Analog design incorporate digital principles Glitch free operation using coding Parallelism and Pipelining! More advanced concepts such as calibration L9: 6.111 Spring 2004 Introductory Digital Systems Laboratory 28 ...
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This note was uploaded on 07/21/2009 for the course EECS 6.111 taught by Professor Prof.ananthachandrakasan during the Spring '04 term at MIT.

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