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l14_project - L14 Quiz Information and Final Project...

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L14: 6.111 Spring 2004 1 Introductory Digital Systems Laboratory L14: Quiz Information and Final Project Kickoff L14: Quiz Information and Final Project Kickoff
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L14: 6.111 Spring 2004 2 Introductory Digital Systems Laboratory Quiz Quiz Quiz Review on Monday, March 29 by TAs 7:30 P.M. to 9:30 P.M. Quiz will be Closed Book on March 31 st (during class time) Covers Problem Sets 1-3, Lectures 1-12, Labs 1-3 Topics to be covered Combinational Logic: Boolean Algebra, Karnaugh Maps, MSP, MPS, dealing with don’t cares Latches and Edge Triggered Registers/Flip-flops z Understand the difference between latches, registers and unclocked memory elements (e.g., SR-Flip Flop) z Different memory types: SR, D, JK, T z Understand setup/hold/propagation delay and how they are computed System Timing (minimum clock period and hold time constraint) z Impact of Clock skew on timing Counters and simple FSMs (understand how the ‘163 and ‘393 work) FSM design (Mealy/Moore, dealing with glitches) Major and Minor FSM construction Combinational and sequential Verilog coding z Continuous assignments, blocking vs. non-blocking, etc.
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L14: 6.111 Spring 2004 3 Introductory Digital Systems Laboratory Quiz (cont.) Quiz (cont.) Tri-states basics Dealing with glitches z When are glitches OK? z How do you deal with glitches in digital system design? (registered outputs, appropriate techniques to gate a clock, etc.) Arithmetic z Number representation: sign – magnitude, Ones complement, Twos complement z Adder Structures: Ripple carry, Carry Bypass Adder (Don’t worry about Carry lookahead adder details) z False Paths and Delay Estimation z Shift/add multiplier, Baugh-Wooley Multiplier (Twos complement multiplication) Memory Basics z Understand differences between DRAM vs. SRAM vs. EEPROM z Understand timing and interfacing to the 6264 Analog building blocks z
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