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l15_print - L15 Custom and ASIC VLSI Integration...

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L15: 6.111 Spring 2004 1 Introductory Digital Systems Laboratory L15: Custom and ASIC VLSI Integration L15: Custom and ASIC VLSI Integration Acknowledgements: - Rabaey, J., A. Chandrakasan, B. Nikolic. Digital Integrated Circuits: A Design Perspective. Prentice Hall, 2003. - Curt Schurgers Materials in this lecture are courtesy of the following people and used with permission.
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L15: 6.111 Spring 2004 3 Introductory Digital Systems Laboratory Layout 101 Layout 101 Cross-Section GND VDD metal poly p+ diff contact frommetal to ndiff L n W n L p W p IN OUT n-type well p-type substrate metal/pdiff contact n+ diff IN OUT V DD S Circuit Representation G G D Layout D ± Follow simple design rules (contract between process and circuit designers) S ( Courtesy of Chris Terman. Used with permission.)
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L15: 6.111 Spring 2004 4 Introductory Digital Systems Laboratory Custom Design/Layout Custom Design/Layout Adder stage 1 Wiring Adder stage 2 Wiring Adder stage 3 Bit slic e 0 e 63 Sum Select Shifter Multiplexers Lo op back B u s From register files / Cache / Bypass To register files / Cache ba ck B Die photograph of the Die photograph of the Itanium integer Itanium integer datapath datapath Bit Bit -slice Design Methodology slice Design Methodology ± Hand crafting the layout to achieve maximum clock rates (> 1Ghz) ± Exploits regularity in datapath structure to optimize interconnects 9- 1 M ux 5- 2- ck1 CARRYGEN SUMGEN + LU 1000um b s0 s1 g64 sum sumb LU : Logical Unit SUMSEL a to Cache node1 REG Itanium has 6 integer execution units like this Itanium has 6 integer execution units like this
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L15: 6.111 Spring 2004 5 Introductory Digital Systems Laboratory The ASIC Approach The ASIC Approach Verilog (or VHDL ) Verilog (or VHDL ) Logic Synthesis Logic Synthesis Floorplanning Floorplanning Placement Placement Routing Routing Tape-out Circuit Extraction Circuit Extraction Pre-Layout Simulation Pre-Layout Simulation Post-Layout Simulation Post-Layout Simulation Structural Structural Physical Physical Behavioral Behavioral Design Capture Design Iteration Most Common Design Approach for Designs up to 500Mhz Clock Rates
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L15: 6.111 Spring 2004 6 Introductory Digital Systems Laboratory Standard Cell Example Standard Cell Example 3-input NAND cell (from ST Microelectronics): C = Load capacitance T = input rise/fall time Power Supply Line (V DD ) Delay in (ns)!! Ground Supply Line (GND) ± Each library cell (FF, NAND, NOR, INV, etc.) and the variations on size (strength of the gate) is fully characterized across temperature, loading, etc.
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L15: 6.111 Spring 2004 7 Introductory Digital Systems Laboratory Standard Cell Layout Methodology Standard Cell Layout Methodology 2-level metal technology Current Day Technology Cell-structure hidden under interconnect layers ±
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This note was uploaded on 07/21/2009 for the course EECS 6.111 taught by Professor Prof.ananthachandrakasan during the Spring '04 term at MIT.

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l15_print - L15 Custom and ASIC VLSI Integration...

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