lab2 - Massachusetts Institute of Technology Department of...

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Massachusetts Institute of Technology Department of Electrical Engineering and Computer Science 6.111 - Introductory Digital Systems Laboratory Laboratory 2 Check Off Sheet Student Name: TA Signature/Date: Part 1: Traffic Light Controller Must Show to TA at beginning of Chekoff FSM State Transition Diagram Verilog Code Printout Be Able to Demonstrate Your Working Lab You will be first asked to demonstrate regular operation with default values You will be asked to reprogram your time values and continue operation You will be asked to demonstrate functionality of Walk Request Register You will be asked to demonstrate functionality of the side sensor Be Able to Respond to any of the Following Questions (and possibly others). You will likely be asked two questions from the following by a TA What could happen if an input were not synchronized to the clock? Describe your synchronizer module and why it is important. Describe your walk request Register. Describe your divider module. What is the difference between a Moore and a Mealy machine? Describe the design flow for your Traffic Light Controller. 1
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Student Name: TA Signature/Date: Part 2: Memory Tester Must Show to TA at beginning of Chekoff Block diagram of memory tester Verilog code printout Be Able to Demonstrate Your Working Lab From reset, demonstrate writing and reading from different locations Demonstrate operation with the MSB of the DATA pin disconnected (D[3]) Be Able to Respond to any of the Following Questions (and possibly others). You will likely be asked two questions from the following by a TA What are possible problems with the address or data glitching when the write on the memory is enabled? Describe your timing for the memory interface. Can you think of a faulty circuit connection between the memory and FPGA that will pass the test? What are the limitations of the proposed simple memory test? 2
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Massachusetts Institute of Technology Department of Electrical Engineering and Computer Science 6.111 - Introductory Digital Systems Laboratory Laboratory 2 Issued: February 18, 2004 Checkoff Due: March 5, 2004 Report Due by 11 AM: March 8, 2004 Part 1: Traffic Light Controller Introduction Part 1 of this lab is a traffic light controller that controls a main street, side street and walk lamps. You will be using a finite state machine to implement this controller. This lab provides you with a design methodology that will be useful in future labs and final projects. This involves planning your design, coding, wiring, and debugging your design. Procedure There are two major phases. The first is the design phase, which consists of reading through the lab, planning, and coming up with a design. Although not required, it is suggested that you sched- ule a conference with your TA to review your design. This will help catch any major mistakes early in the process. The next phase is to implement the first part of the lab using the FPGA. After you verify the traf-
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This note was uploaded on 07/21/2009 for the course EECS 6.111 taught by Professor Prof.ananthachandrakasan during the Spring '04 term at MIT.

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lab2 - Massachusetts Institute of Technology Department of...

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