lab3 - Massachusetts Institute of Technology Department of...

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Massachusetts Institute of Technology Department of Electrical Engineering and Computer Science 6.111 - Introductory Digital Systems Laboratory Laboratory 3 Check Off Sheet Student Name: TA Signature/Date: Part 1: Analog Interface You must show a TA the following at the beginning of the analog check off State transition diagram of your FSM(s). Verilog code. Timing diagrams for your D/A and A/D. Be Able to Demonstrate Your Working Lab You will be asked to demonstrate the correct performance of your A/D and D/A by simply reconstructing the signal sampled by your A/D at the output of your D/A. Be Able to Respond to any of the Following Questions (and possibly others) What are the critical timing constraints of your A/D and D/A system? Explain the operation and importance of your tri-state bus. Can you have glitches on the control inputs CS, CE, R/W for the A/D? Can you have glitches on the control inputs CS, CE for the D/A? 1
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Student Name: TA Signature/Date: Part 2: Complete Digital Filter (including analog blocks) You must show a TA the following at the beginning of the analog check off Block diagram for your system. State transition diagrams for your major-minor FSM structure. Verilog code printout. Be Able to Demonstrate Your Working Lab From reset, demonstrate that you can filter an input signal with any of the 4 impulse responses provided. Be Able to Respond to any of the Following Questions (and possibly others) Describe the critical timing issues of your system. What are the possible problem(s) with the shared tristate bus structure? For the clock frequency you used, what is the fastest sampling rate possible? Can you suggest ways to improve the throughput of the system? 2
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Massachusetts Institute of Technology Department of Electrical Engineering and Computer Science 6.111 - Introductory Digital Systems Laboratory Laboratory 3 - Finite Impulse Response Filter Issued: March 3, 2004 Analog Checkoff: March 19, 2004 Final Checkoff and Report Due: April 2, 2004 1. Introduction You will design a 16-tap Finite Impulse Response Filter (FIR) in this lab, suitable for filtering inputs from a signal generator or audio signals from a music player or microphone. Like the previous labs, you will need to design finite state machines to control your subsystems. Additionally, you will need to instantiate some modules and build controllers to interface an analog to digital converter and a digital to analog con- verter to your FPGA. 2. Procedure This lab consists of three parts. The first part is the design phase, which is very similar to the previous labs. You should read through the lab and plan your design. It will be helpful to schedule a design conference with your TA or the professor to help with your design.
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This note was uploaded on 07/21/2009 for the course EECS 6.111 taught by Professor Prof.ananthachandrakasan during the Spring '04 term at MIT.

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lab3 - Massachusetts Institute of Technology Department of...

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