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# pset2 - Massachusetts Institute of Technology Department of...

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Massachusetts Institute of Technology Department of Electrical Engineering and Computer Science 6.111 – Introductory Digital Systems Laboratory Problem Set 2 Problem Set Issued: Feb. 18, 2004 Problem Set Due: Feb. 27, 2004 Comments: This problem set is intended to prepare you for Laboratory 2 which is a Traffic Light Controller and Memory Tester. By working through this problem set you should be able to design simple counter and memory circuits in both hardware and software, design finite state machines, and design and use a testbench to simulate your own Verilog code in ModelSim. Verilog coding and its simulation in ModelSim are major components of this lab. A tutorial for using ModelSim is provided in the Software Tools section of the course webpage. We expect this problem set to take significantly more time than Problem Set 1 so please start early. The upside to the extra work put into this problem set is that you will be able to reuse some of the Verilog modules created here for your Lab 2 (namely the one second timer and the memory tester). Problem 1: Counters Part (a) Using 74LS163 counters and a 1.8432 MHz clock design a circuit that divides the clock by counting to 128 thus producing a 14.4 KHz clock. To verify your design you may want to build this simple circuit using your lab kit although this is not a requirement. The 74LS163 is a four-bit counter whose data sheet can be found on the course webpage under Lab1. Hint: 128 factors into 16 and 8. Part (b) How many LS163s would it take to produce a 1 Hz clock? Hint: What is the binary representation of 1843200? Part (c) What is the difference between an LS393 and an LS163? Part (d) In this part of the problem you will be creating a Verilog module which will be used later in this problem set and in Lab 2.

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