pset3s - Massachusetts Institute of Technology Department...

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Massachusetts Institute of Technology Department of Electrical Engineering and Computer Science 6.111 – Introductory Digital Systems Laboratory Problem Set 3 Solutions Problem Set Issued: March 3, 2004 Solutions Issued: March 19, 2004 Problem 1 – Convolution Part (a) We can answer this problem using the convolution sum or the flip and shift method. 9 8 8 y a [n] 3 3 1 1 012 3 45 6 n Part (b) y b [n] 1 1 0 2 4 6 n -1 -1 -11 Part (c) X c [n] h c [n] y c [n] 4 2 2 2 2 2 2 1 1 * = 0123 n -1 01 n -1 3 n -2
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Part (d) For this part we consider a multiply-accumulate module of the form similar to the one to be used in Lab 3. The multiplication of two eight-bit numbers requires 16 output bits. The fact that we are using a 10-tap filter means that we will need to accumulate ten 16-bit numbers. The summation of ten product terms affects the width of the adder by requiring the addition of the binary representation of 10 (4’b1010) with the width of the multiplier output (16 bits). Thus we have 16 + 4 = 20 bits. Problem 2 – Two’s Complement Multiplier Several methods of designing an 8x8 multiplier are possible for this problem. The easiest approach is to use unsigned multiplication using the * multiply operation in Verilog and then accounting for the sign on the MSB. The Verilog code and screen capture for this approach are provided below. In this solution we present both a blocking solution (asynchronous) and a non- blocking (synchronous) solution. The synchronous solution pipelines the logic from the asynchronous solution. There is a delay of four clock cycles associated with using the synchronous multiplier. Please note that we account for both zero representations in magnitude representation by checking for this condition on the input y. Other approaches are possible for answering this question. One possible alternative was to implement an 8x8 Baugh-Wooley multiplier based off the 4x4 implementation presented in Lecture 8. Asynchronous Multiplier //8x8 Multiplier (Two's Complement x Magnitude) module twos_compliment_multiplier (x, y, z); input [7:0] x, y; output [15:0] z; wire [7:0] x_neg, y_neg; wire [15:0] z_pos, z_neg, z; assign x_neg = (x == 8'b0) ? 8'b0: (~x + 1); assign y_neg = (y == 8'b0 || y == 8’b10000000) ? 8'b0: (~y + 1); assign z_pos = (x[7] ? x_neg : x) * (y[7] ? y_neg : y); assign z_neg = (z_pos == 8'b0) ? 8'b0 : (~z_pos + 1); assign z = (x[7] ^ y[7]) ? z_neg : z_pos; endmodule 2
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Synchronous Multiplier module synch_twosmult (clk, reset, x, y, z);
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This note was uploaded on 07/21/2009 for the course EECS 6.111 taught by Professor Prof.ananthachandrakasan during the Spring '04 term at MIT.

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pset3s - Massachusetts Institute of Technology Department...

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