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ECE442_Sample_Final_2

ECE442_Sample_Final_2 - ECE442 Sample Final 2 1 Consider...

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ECE442 Sample Final 2 1. Consider the following cross-coupled latch as implemented in a CMOS technology (sketch it). Let Kn' = 20 µ A/volts2, Kp' = 10 µ A/volts2, Wn = 12 µ m, Wp = 24 µ m, Ln = Lp = 6 µ m, Vtn = -Vtp = 1 volts and VDD = 5 volts. a) Plot the transfer characteristic of each inverter, i.e. Vx versus Vw and Vz versus Vy. Determine the output of each inverter at input voltages of 1, 1.5, 2, 2.25, 2.5, 2.75, 3, 3.5, 4, 4.5 and 5 volts b) Use the characteristics in part "a" to determine the loop voltage transfer curve of the latch, i.e. Vz versus Vw. Find the coordinates of the three operating points (Two stable, one unstable) as discussed in class 2. Design the following Boolean function F=(A+BC+DE)* using Dynamic Logic. Assume that the logic is driving a 50fF capacitive load and that the sizing of the PMOS and the NMOS transistors are 20/1 and 10/1 respectively. Estimate the worst-case T PHL . 3. Design the following logic function (create a truth table) Y = AB*+BC+C* using the following three technologies. Which one would result in minimum

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ECE442_Sample_Final_2 - ECE442 Sample Final 2 1 Consider...

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