Sample Test I - ECE 3060 Advanced Digital Design and VLSI...

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ECE 3060 Advanced Digital Design and VLSI Sample Test 1 1. Gate Design a) Design an AOI21 Gate. Give the switching function for the pullup (F sp ) and for the pulldown (F sn ) and show the transistor schematic and a gate symbol for this device. b) Suppose F = AB+ C(D+E) . Design a complex gate and cell that implements F using the paral- lel diffusion layout style. Show the transistor schematic, corresponding graphs, Euler paths, and stick diagram. 2. Transistor Operation and Design Rules. Answer in a sentence or three. a) Why does the channel tilt in a MOSFET when V gs > V T and V ds > 0 . b) How would a process engineer be able to control the width of a depletion region at a given bias voltage? What would happen if a drain substrate depletion region extended all the way from drain to source? c) Why is the active region in a substrate contact doped P+? d) What is the rationale for the minimum separation rule between unrelated polysilicon? 3. Datapath
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This note was uploaded on 07/30/2009 for the course ECE 3060 taught by Professor Shimmel during the Spring '07 term at Georgia Institute of Technology.

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Sample Test I - ECE 3060 Advanced Digital Design and VLSI...

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