hw5_sol - ABCD= ‘010*’ or ABCD= ‘01*0’(b Find a...

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ECE 3060 Hw5 Solution - Summer 2009 1. Consider the following state diagram: (a) Derive a state transition table
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(b) Perform state minimization as described in lecture. Π1 = {{S1,S4,S6},{S2,S5},{S3}} Π2 = {{S1},{S4},{S6},{S2,S5},{S3}} Π3 = {{S1},{S4},{S6},{S2,S5},{S3}} Therefore S2 and S5 are equivalent. (c) Draw the resulting state diagram if different 2. Suppose a signal x is known to be Sφ1Vφ2 and a signal y is Sφ2Vφ1. What is the strongest timing assertion that can be made on z = x y ? The strongest common assertion on x and y is Vφ1Vφ2.
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3. Consider the following circuits: (a) Find a test vector to detect a s-a-1 on x.
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Unformatted text preview: ABCD= ‘010*’ or ABCD= ‘01*0’ (b) Find a test vector to detect a s-a-0 on y. ABCD= ‘1*0*’ or ABCD= ‘1**0’ or ABCD= ‘*10*’ or ABCD= ‘*1*0’ (c) Find a test vector to detect a s-a-1 on the upper input to the gate labeled G1. x1x2x3 = ‘*1*’ (d) Find a test vector to detect a s-a-0 on the upper input to the gate labeled G1. Not observable because x1x2 = ‘00’ is needed to drive a ‘1’ on the fault, but that pattern also masks the fault since the lower input of G1 would then be a ‘1’ (e) Find a test vector to detect a s-a-0 on x3. Also not observable....
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This note was uploaded on 07/30/2009 for the course ECE 3060 taught by Professor Shimmel during the Spring '07 term at Georgia Tech.

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hw5_sol - ABCD= ‘010*’ or ABCD= ‘01*0’(b Find a...

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