hw4_sol

# hw4_sol - ECE 3060 VLSI and Advanced Digital Design...

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Unformatted text preview: ECE 3060 VLSI and Advanced Digital Design Homework 6 Solution 1.Consider a standard cell library consisting of the following cells: Cell Area Delay Input load INV 3 1+l 1 SINV2 6 1+0.5l 2 SINV4 10 1+0.25l 4 NOR2 7 2+2l 2 NAND2 5 2+1.5l 1 OAI21 7 3+2l 2 (i) Using INV and NAND2 as base function, draw pattern trees of the cells in the library. Spring 2009 Due: 7.4.2009 Prof. David Schimmel Sections A Given the following decomposition of G: A B C E F D G (ii) Find a minimum area mapping of G. (iii) Node Match Cost q INV(A) 3 r INV(B) 3 s NAND2(C,D) 5 t INV(F) 3 u NAND2(q,r) 3+3+5=11 v NAND2(E,t) 3+5=8 w NAND2(u,s) OAI21(A,B,s) 11+5+5=21 5+7=12 x INV(w) 12+3=15 Node Match Cost y INV(v) 8+3=11 z NAND2(x,y) 15+11+5=31 G INV(z) NOR2(w,v) 31+3=34 12+8+7=27 Note: SINV cells match, but are never used when minimizing area, so are suppressed. (iv) Find a minimum delay mapping of G assuming a ¡nal load of 2, and inputs (A-F) are driven with a delay of 1+l....
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## This note was uploaded on 07/30/2009 for the course ECE 3060 taught by Professor Shimmel during the Spring '07 term at Georgia Tech.

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hw4_sol - ECE 3060 VLSI and Advanced Digital Design...

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