This preview has intentionally blurred sections. Sign up to view the full version.
View Full DocumentThis preview has intentionally blurred sections. Sign up to view the full version.
View Full DocumentThis preview has intentionally blurred sections. Sign up to view the full version.
View Full DocumentThis preview has intentionally blurred sections. Sign up to view the full version.
View Full Document
Unformatted text preview: and will be shorted together an unacceptable fraction of the time. â€¢ No required polymetal spacing: Theyâ€™re on two different layers. â€¢ 1 Î» of diffusion and metal surrounding cut: To ensure that contact cut reliably aligns with diffusion region and metal even with layer/mask misregistration. â€¢ 2 Î» overhang of poly at transistor gates: Transistor must not be shorted even with a 1 Î» shift in the respective layers 6. Design a complex gate cell (transistor schematic and stick diagram) for the following functions. Use the parallel diffusion (Euler path) style of layout. (a) C B A C B A F * * = + + = A B C A B C F (b) E D C B A F * * * + = A B C A B C D E D E F (c) ) )( ( D C B A CD AB F + + = + = A B C D F A B C D (d) AC C A B AC BC AB F + + = + + = ) (...
View
Full
Document
This note was uploaded on 07/30/2009 for the course ECE 3060 taught by Professor Shimmel during the Spring '07 term at Georgia Tech.
 Spring '07
 Shimmel

Click to edit the document details