hw1_sol - and will be shorted together an unacceptable...

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ECE 3060 Hw1 Solution – Summer 2009 1. Given the function , write a truth table for F, and use a K-map to find a minimum sum of products expression for F. F= wx z + wx y + wy z + wxz +xyz + w xy + w yz +x yz
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2. For each of the following functions, find an expression for the function and the complement of the function using only literals, OR, and AND. ) ( ) ( ) )( ( ) )( ( ) ( ) )( ( ) ( ) ( E D C B A DE C AB F DE C AB DE C AB F c DE ABC F E D C B A F b ABC F C B A ABC F a + + = + = + + = + = + = + + + = = + + = = 3. Implement each function in 2 as a CMOS complex gate (show the transistor schematic). (a) A B C A B C F
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(b) A B C A B C D E D E F (c) C C D’ E’ F A’ B’ A’ B’ D’ E’
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4. Solutions below for Wolf 2-1 from 3rd edition of book.
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5. Solutions below for Wolf 2-5 from 3rd edition of book. 2 λ poly-poly spacing: This rule is derived from the resolution limit of the composition of all process steps (mask, etch etc). Poly line which are closer may not be reliably distinct,
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Unformatted text preview: and will be shorted together an unacceptable fraction of the time. No required poly-metal spacing: Theyre on two different layers. 1 of diffusion and metal surrounding cut: To ensure that contact cut reliably aligns with diffusion region and metal even with layer/mask mis-registration. 2 overhang of poly at transistor gates: Transistor must not be shorted even with a 1 shift in the respective layers 6. Design a complex gate cell (transistor schematic and stick diagram) for the following functions. Use the parallel diffusion (Euler path) style of layout. (a) C B A C B A F * * = + + = A B C A B C F (b) E D C B A F * * * + = A B C A B C D E D E F (c) ) )( ( D C B A CD AB F + + = + = A B C D F A B C D (d) AC C A B AC BC AB F + + = + + = ) (...
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hw1_sol - and will be shorted together an unacceptable...

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