hw2soln - Summer 2009 ECE 3060 Prof. David Schimmel...

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Unformatted text preview: Summer 2009 ECE 3060 Prof. David Schimmel Sections A VLSI and Advanced Digital Design Homework 2 Solution ECE3060 - Fall a gate 1. We have seen in lecture that the delay of 2005 with input capacitance Cin drivHW # 6 Show that ing a load of Cout is d = gh + p = f + p . - Solutions f = RoutCout , where Rout is the worst case resistance of the pullup and pulldown networks. Problem 1: d = f + p; f = g.h => d = g.h + p f = g.h ; Also: Rt = ! * Rout; Ct = Cin/! ; And : g = (Rt * Ct) / (Rinv * Cinv) , h = (Cout/Cin) Replacing g, h in f gives: f = (Rt * Ct) / (Rinv * Cinv) * (Cout/Cin) (" Units) Also: f (abs) = (Rinv * Cinv) * f (Seconds) Replacing f in f(abs) gives: f (abs) = (Rinv * Cinv) * (Rt * Ct) / (Rinv * Cinv) * (Cout/Cin) (Seconds) f (abs) = (Rt * Ct) * (Cout/Cin) (Seconds) Replacing Rt = ! * Rout; Ct = Cin/! gives: f (abs) = ! Rout * Cin / ! * (Cout/ Cin) (Seconds) f (abs) = Rout * Cin * (Cout/ Cin) (Seconds) f (abs) = Rout Cout (Seconds) 2. Calculate the logical effort g for the following complex gates (show your work). Assume that the width of a pfet in an inverter is twice the width of an nfet in Review: that general formula for g is: g = "gate/ "inv = (Rdrive * Cin)gate / (Rdrive * Cin)inv The inverter. = Rout Cout/(Rinv.Cinv) = = Rt Ct/(Rinv.Cinv) if (Rdrive)gate = (Rdrive)inv => g = Cin/Cinv (Lemma 2) if (Cin)gate = (Cin)inv => g = Rout/Rinv(Lemma 1: Normalized Rout) Vdd 2(R) 1(R) (a) (i) z = (q.r.s.t.u.v)' NAND6 z = qrstuv (NAND6) g = Cin/Cinv = (2+6)/3 = 8/3 Vdd q q r s t u v 2(R)2(R) 6((1/6)R) 6((1/6)R) 6((1/6)R) 6((1/6)R) 6((1/6)R) 6((1/6)R) r 2(R) s 2(R) t 2(R) u 2(R) v f (b) (ii) z = (q+r+s+t+u+v+w+x)' (NOR8) z = q + r + s + t + u + v + w + x NOR8 g = Cin/Cinv = (16+1)/3 = 17/3 Vdd x w v u t i1 16((1/8)R) 16((1/8)R) 16((1/8)R) 16((1/8)R) 16((1/8)R) 16((1/8)R) i2 s r i3 16((1/8)R) 16((1/8)R) 1(R)1(R) r 1(R) s 1(R) t 1(R) u 1(R) s 1(R) v 1(R) w 1(R) f x q q z = (q+r+s+t+u+v)' NOR6 g = Cin/Cinv = (12+1)/3 = 13/3 Vdd v u t s 12((1/6)R) 12((1/6)R) 12((1/6)R) 12((1/6)R) (c) (iii)qrst + uvwx (AOI44) z(iii)zz==(q.r.s.t+u.v.w.x)' AOI44 = (q.r.s.t+u.v.w.x)' AOI44 g = Cin/Cinv = (4+4)/3 = 8/3 g = Cin/Cinv = (4+4)/3 = 8/3 Vdd Vdd q q u u q q r r s s t t 4((1/2)R) 4((1/2)R) 4((1/2)R) 4((1/2)R) 4((1/2)R) 4((1/2)R) 4((1/2)R) 4((1/2)R) 4((1/4)R) 4((1/4)R) 4((1/4)R) 4((1/4)R) 4((1/4)R) 4((1/4)R) 4((1/4)R) 4((1/4)R) r 4((1/2)R) r 4((1/2)R) v 4((1/2)R) v 4((1/2)R) s 4((1/2)R) t s 4((1/2)R) w 4((1/2)R) w 4((1/2)R) 4((1/4)R) 4((1/4)R) 4((1/4)R) 4((1/4)R) 4((1/4)R) 4((1/4)R) 4((1/4)R) 4((1/4)R) x u v w t xf u v w f x x (d) (iv) z = ((q+r+s).(t+u+v).(w+x+y))' OAI333 z(iv) z+= ((q+r+s).(t+u+v).(w+x+y))' OAI333 = (q r + s)(t + u + v)(w + x + y) (OAI333) g = Cin/Cinv = (6+3)/3 = 3 g = Cin/Cinv = (6+3)/3 = 3 Vdd s Vdd 6((1/3)R) 6((1/3)R) v 6((1/3)R) v u t y v s s r r q q w w t t q q 6((1/3)R) 6((1/3)R) 6((1/3)R) 6((1/3)R) 6((1/3)R) 6((1/3)R) 6((1/3)R) 6((1/3)R) 6((1/3)R) 3((1/3)R) 3((1/3)R) 3((1/3)R) 3((1/3)R) 3((1/3)R) 3((1/3)R) 6((1/3)R) 3((1/3)R) 3((1/3)R) 3((1/3)R) 3((1/3)R) 3((1/3)R) 3((1/3)R) v 6((1/3)R) u 6((1/3)R) u 6((1/3)R) t 6((1/3)R) t 6((1/3)R) x 3((1/3)R) u r v u tf f y v s x u r 3((1/3)R) 3((1/3)R) 3((1/3)R) 3((1/3)R) 3((1/3)R) 3. Repeat 2. assuming that the width of pfet and the nefet in an inverter are identical. Problem 3: Size(PFET) = Size (NFET); Cinv = 1 + 1 = 2 CFET; R = Rn Vdd 1(2R) 1(R) (a) (i) qrstuv (NAND6) z = z = (q.r.s.t.u.v)' NAND6 g = Cin/Cinv = (1+6)/2 = 7/2 Vdd q q r s t u v 1(2R) 1(2R) 6((1/6)R) 6((1/6)R) 6((1/6)R) 6((1/6)R) 6((1/6)R) 6((1/6)R) r 1(2R) s 1(2R) t 1(2R) u 1(2R) v f (b) z = q + = + s + t + u + v + w + x NOR8 (ii) z r (q+r+s+t+u+v+w+x)' (NOR8) g = Cin/Cinv = (8+1)/2 = 9/2 Vdd x w v u t i1 8((1/4)R) 8((1/4)R) 8((1/4)R) 8((1/4)R) 8((1/4)R) 8((1/4)R) i2 s r i3 8((1/4)R) 8((1/4)R) 1(R)1(R) r 1(R) s 1(R) t 1(R) u 1(R) s 1(R) v 1(R) w 1(R) f x q q z = (q+r+s+t+u+v)' NOR6 g = Cin/Cinv = (6+1)/2 = 7/2 Vdd v u t s 6((1/3)R) 6((1/3)R) 6((1/3)R) 6((1/3)R) (c) (iii) z = (q.r.s.t+u.v.w.x)' AOI44 z(iii) z =+ uvwx (AOI44) AOI44 = qrst (q.r.s.t+u.v.w.x)' g = Cin/Cinv = (4+2)/2 == 3 g = Cin/Cinv = (4+2)/2 3 Vdd Vdd q q u u 2(R) 2(R) 2(R) 2(R) 2(R) 2(R) r r v 2(R) 2(R) 2(R) s w s w 2(R) 2(R) t 2(R) t x f u v w x f 2(R) 4((1/4)R) 4((1/4)R) 4((1/4)R) 4((1/4)R) 2(R) v 2(R) 2(R) x u v w x q r s t q r s t 4((1/4)R) 4((1/4)R) 4((1/4)R) 4((1/4)R) 4((1/4)R) 4((1/4)R) 4((1/4)R) 4((1/4)R) 4((1/4)R) 4((1/4)R) 4((1/4)R) 4((1/4)R) (iv) z = ((q+r+s).(t+u+v).(w+x+y))' OAI333 (d) z(iv) z+= ((q+r+s).(t+u+v).(w+x+y))' OAI333 = (q r + s)(t + u + v)(w + x + y) (OAI333) g = Cin/Cinv = (3+3)/2 = 3 Vdd g = Cin/Cinv = (3+3)/2 = 3 s Vdd 3((2/3)R) 3((2/3)R) 3((2/3)R) 3((2/3)R) v u 3((2/3)R) v u t y s r 3((2/3)R) 3((2/3)R) v 3((2/3)R) 3((2/3)R) v u f r q q w w t q t 3((2/3)R) 3((2/3)R) 3((2/3)R) 3((1/3)R) 3((1/3)R) 3((1/3)R) 3((1/3)R) 3((1/3)R) 3((2/3)R) 3((2/3)R) 3((2/3)R) 3((1/3)R) 3((1/3)R) 3((1/3)R) 3((1/3)R) 3((1/3)R) 3((2/3)R) t u3((2/3)R) 3((2/3)R) x t 3((1/3)R) t f y v s 3((1/3)R) v u x 3((1/3)R) r u 3((1/3)R) 3((1/3)R) s q 3((1/3)R) 3((1/3)R) r 3((1/3)R) 4.Size the following circuits and calculate optimal delay using the method of LE assuming equal worst case rise and fall time. (a) Assume Cin = Cinv and Cout = 45Cinv . Repeat for Cout = 400Cinv . Problem 1: HW # 7 - Solutions i.a)Cin = Cinv; Cout = 45 Cinv; Rise Time = Fall Time ; Cinv = 2 + 1 = 3 CFET; Problem 1: i.a)Cin = Cinv; Cout = 45 Cinv; Rise Time = Fall Time ; Cinv = 2 + 1 = 3 CFET; ECE3060 - Fall 2005 HW # 7 - Solutions Problem 1: i.a)Cin = Cinv; Cout = 45 Cinv; Rise Time = Fall Time ; Cinv = 2 + H = Cout/Cin = 45;N = 2 g1 Cout/Cin = 45;N = 2 H = = (4+2)/3; g2 = (6+1)/3 G ! (gi) g2 = (6+1)/3 g1 = (4+2)/3;= g1.g2 = 14/3 G = ! (gi) ==1 B = ! (bi) g1.g2 = 14/3 F = GBH 14/3 * 45 = 210 B = ! (bi) =1 fhat = F^(1/N) * 14.49 F = GBH = 14/3 = 45 = 210 fhat= 4 Pinv; p214.49 p1 = F^(1/N) = = 3 Pinv p1 = 4 Pinv; p2 = 3 Pinv P = " (pi) = p1+p2 = 7 Pinv # 7 $ P = " (pi) = p1+p2 = 7 Pinv # 7 $ Dhat = N *fhat + P = 36 $ H = Cout/Cin = 45;N = 2 g1 = (4+2)/3; g2 = (6+1)/3 G = ! (gi) = g1.g2 = 14/3 B = ! (bi) =1 F = GBH = 14/3 * 45 = 210 fhat = F^(1/N) = 14.49 p1 = 4 Pinv; p2 = 3 Pinv P = " (pi) = p1+p2 = 7 Pinv # 7 $ Dhat = N *fhat + P = 36 $ Df = " (fi); D = Df + P = 35.98 $ y = g2.Cout / fhat = 7.24 Cinv; z = g1.y/ fhat = 1 Cinv y = g2.Cout / fhat = 7.24 Cinv; z = g1.y/ fhat = 1 Cinv Df = " (fi); D = Df + P = 35.98 $ Repeat for Cout = 400Cinv . * Total Tr. the sizes is just done to see how rounding can affect Delay. Actually, sizes Rounding 30.00 !(gbh+p) 36.00 change after determining transistor sizes. Use the rounding can affectsizes to find sizing sizes Path Tr. 14.00 * Rounding the sizes is just done to see how calculated transistor Delay. Actually, Plus minor 16.00 from output to determining transistor sizes.the previous stage; however, Tr. sizes to find sizing change after input to determine the size of Use the calculated transistor Total Tr. 30.00 variations doesn't change determine the size of the previous stage; however, minor the delay so much. from output to input to * Rounding the sizes is just done to see how rounding can affect Delay. variations doesn't change the delay so much. change after determining transistor sizes. Use the calculated transistor s from output to input to determine the size of the previous stage; howeve variations doesn't change the delay so much. NAND4+NOR3 NAND4+NOR3 * * Dhat = h(i) +g(i)*b(i)*h(i) T(i) *fhat P = Parameters g(i) size(i) [size(i)] Ng(i)*b(i)*h(i) 36 $ Parameters g(i) p(i) p(i) b(i) b(i) size(i) [size(i)] h(i) T(i) = " 7.00 14.00 = 35.98 $ Cout 45.00gz gz 2.00 pz pz bz bz 2.00 4 1 1.00 1Df 7.00 (fi); D = Df + P14.00 1 8 Cout 45.00 4 1 1.00 8 Cin 1.00 2.33 1 7 6 Cin 1.00 gy gy 2.33 py py by by 3 3 1 7.25 7.25 7y = g2.Cout / fhat = 7.24 Cinv; z = g1.y/ fhat = 1 Cinv 6.43 6.43 15.00 15.00 6 H 45.00 H 45.00 NAND4+NOR3 * N 2.00 N 2.00 Parameters g(i) p(i) b(i) size(i) P 7.00 P 7.00 Cout 45.00 gz 2.00 pz 4 bz 1 1.00 G 4.67 G 4.67 Cin 1.00 gy 2.33 py 3 by 1 7.25 B 1.00 B 1.00 H 45.00 F 210.00 N 2.00 F 210.00 N_Hat 3.86 P 7.00 N_Hat 3.86 f 14.49 G 4.67 f 14.49 D 35.98 B 1.00 D 35.98 !(gbh) 29.00 F 210.00 !(gbh) 29.00 !(gbh+p) 36.00 N_Hat 3.86 !(gbh+p) 36.00 Path Tr. 14.00 f 14.49 Path Tr. 14.00 Plus Tr. 16.00 D 35.98 Total Tr. 30.00 Plus Tr. 16.00 !(gbh) 29.00 [size(i)] 1 7 h i.b) Cin = Cinv; Cout = 400 Cinv; Rise Time = Fall Time ; Cinv = 2 + 1 = 3 CFET; H = Cout/Cin = 400 N=2 g1 = (4+2)/3; g2 = (6+1)/3 G = ! (gi) = g1.g2 = 14/3 B = ! (bi) =1 F = GBH = 14/3 * 400 = 5600/3 " 1866.67 fhat = F^(1/N) = 43.20 p1 = 4 Pinv; p2 = 3 Pinv P = # (pi) = p1+p2 = 7 Pinv " 7 $ Dhat = N *fhat + P = 93.41 $ NAND4+NOR3 * Parameters g(i) p(i) b(i) size(i) [size(i)] h(i) g(i)*b(i)*h(i) Cout 400.00 gz 2.00 pz 4 bz 1 1.00 1 22.00 44.00 Cin 1.00 gy 2.33 2005 3 by py 1 21.60 22 18.18 42.42 October 5, H 400.00 N 2.00 P 7.00 Due: Wednesday, 26G October, 2005 4.67 at 4:30PM in CCB 360 B 1.00 F 1866.67 1. Resize the following circuits and calculate optimal delay using the method of LE assuming N_Hat 5.43 equal worst case rise and fall time. f 43.20 D 93.41 C out (i) Assume C!(gbh)C inv and 86.42 = 45C inv . Repeat for C out = 400C inv . in = !(gbh+p) Path Tr. Plus Tr. 93.42 14.00 16.00 ECE 3060 VLSI and Advanced Digital Design Homework 7 D = Df + P = 93.42 $ y = g2.Cout / fhat = 21.60 Cinv; z = g1.y/ fhat = 1 Cinv Df = # (fi) T(i) 8 6 * Rounding the sizes is just done to see how rounding can affect Delay. Actually, sizes change after determining transistor sizes. Use the calculated transistor sizes to find sizing from output to input to determine the size of the previous stage; however, minor C out variations doesn't change the delay so much. (b) Assume Cin = Cinv and Cout = Cinv . Repeat for Cout = 250Cinv . (ii) Assume C in = C inv and C out = C inv . Repeat for C out = 250C inv C out 2. Sketch a design for 6-64 decoder whose outputs must drive 500 C inv of load. You do not need to fully explore the design space. However, you should indicate how many levels of logic you expect, and what implementation you think is likely best, and why. Assume that your address lines are driven by minimum size inverters, and worst case rise is about twice as long as worst case fall time (min size nfet and pfet in the prototype inverter). Problem 1: ii.a) Cin = Cinv; Cout = Cinv; Rise Time = Fall Time ; Cinv = 2 + 1 = 3 CFET; H = Cout/Cin = 1;N = 4 g1 = (4+2)/3 = 2; g2 = 1; g3 = (3+2)/3 = 5/3; g4 = 1 G = ! (gi) = g1.g2.g3.g4 = 10/3 B = ! (bi) =1 F = GBH = 10/3 * 1 = 10/3 fhat = F^(1/N) = 1.35 p1 = 4 Pinv ; p2 = 1 Pinv, p3 = 3 Pinv, p4 = 1Pinv P = " (pi) = p1+p2+p3+p4 = 9 Pinv # 9 $ Dhat = N *fhat + P = 14.40 $ Df = " (fi); D = Df + P = 14.67 $ w = g4.Cout / fhat = .074 Cin; x = g3. w/ fhat = .9128; y = g2.x / fhat = .74 Cinv; z = g1.y / fhat = 1 Cinv; NAND4+INV+NAND3+INV * Parameters Cout 1.00 Cin 1.00 H 1.00 N 4.00 P 9.00 G 3.33 B 1.00 F 3.33 N_Hat 0.87 f 1.35 D 14.40 !(gbh) 5.67 !(gbh+p) 14.67 Path Tr. 18.00 Plus Tr. 20.00 Total Tr. 38.00 g(i) gz gy gx gw p(i) pz py px pw b(i) bz by bx bw size(i) 1.00 0.68 0.91 0.74 [size(i)] 1 1 1 1 h(i) 1.00 1.00 1.00 1.00 g(i)*b(i)*h(i) 2.00 1.00 1.67 1.00 T(i) 8 2 6 2 2.00 1.00 1.67 1.00 4 1 3 1 1 1 1 1 * Rounding the sizes is just done to see how rounding can affect Delay. Actually, sizes change after determining transistor sizes. Use the calculated transistor sizes to find sizing from output to input to determine the size of the previous stage; however, minor variations doesn't change the delay so much. Problem 1: Repeat for Cout = 250Cinv . ii.b) Cin = Cinv; Cout = 250 Cinv; Rise Time = Fall Time ; Cinv = 2 + 1 = 3 CFET; H = Cout/Cin = 250; N = 4 g1 = (4+2)/3 = 2; g2 = 1; g3 = (3+2)/3 = 5/3; g4 = 1 G = ! (gi) = g1.g2.g3.g4 = 10/3 B = ! (bi) =1 F = GBH = 10/3 * 250 = 2500/3 " 833.33 fhat = F^(1/N) = 5.37 p1 = 4 Pinv ; p2 = 1 Pinv, p3 = 3 Pinv, p4 = 1Pinv P = # (pi) = p1+p2+p3+p4 = 9 Pinv " 9 $ Dhat = N *fhat + P = 30.49 $ Df = # (fi); D = Df + P = 30.58 $ w = g4.Cout / fhat = 46.53 Cin; x = g3. w/ fhat = 14.43; y = g2.x / fhat = 2.69 Cinv; z = g1.y / fhat = 1 Cinv; NAND4+INV+NAND3+INV * Parameters H 250.00 N 4.00 P 9.00 G 3.33 B 1.00 F 833.33 N_Hat 4.85 f 5.37 D 30.49 !(gbh) 21.58 !(gbh+p) 30.58 Path Tr. 18.00 Plus Tr. 20.00 Total Tr. 38.00 g(i) gz gy gx gw p(i) pz py px pw b(i) bz by bx bw size(i) 1.00 2.69 14.43 46.53 [size(i)] 1 3 14 47 h(i) 3.00 4.67 3.36 5.32 g(i)*b(i)*h(i) 6.00 4.67 5.60 5.32 T(i) 8 2 6 2 2.00 1.00 1.67 1.00 4 1 3 1 1 1 1 1 * Rounding the sizes is just done to see how rounding can affect Delay. Actually, sizes change after determining transistor sizes. Use the calculated transistor sizes to find sizing from output to input to determine the size of the previous stage; however, minor variations doesn't change the delay so much. 5. Sketch a design for 6-64 decoder whose outputs must drive 800Cinv of load. You do not need to fully explore the design space. However, you should indicate how many levels of logic you expect, and what implementation you think is likely best, and why. Assume that your address lines are driven by minimum size inverters. Since F will be quite large, with a large number of levels of logic, assume that we will use only NAND2 and inverter gates. First, the circuit will be non-symmetric, since 6 is not a power of two. Assume a NAND-INV-NAND-INV-NAND which would give an 8 input AND implementation if the tree were complete. This implementation has lowest possible G. However, one side of the tree will be NAND-inv-inv-inv, which will give us the 6-input AND function needed for a 6-64 decoder. Now, G = (4 / 3)3 = 64 / 27 , B=2*32=64 (because every variable appears in every term in true or complemented form), and H=800. Therefore F=GBH=121,363. Then N = round(log3.6F) = 9 . Now, since we'll have very high branching, let's calculate how many levels we need to drive the branching load. Assume the first level of NAND2 gates are minimum size (2/3 Cinv). Then the branching load on any input will be 32(2/3)=21.3 Cinv, and we'll need about 3 levels of logic to drive that load. Here is a sketch of the design, showing branching, and both sides of the AND tree. Note that we are minimizing delay over the 9 stage path, and the size of the inverters sized at 32z is fixed when we size the NAND2 with size z. 4-input AND term a0 y z 32 way branch y 32z 32 way branch y 32z 32 way branch a5 y z 32 way branch 2 input AND term ^ Calculating worst case delay for this circuit, we have f = F1/9 = 3.7 , and ^ D = 9f + P +2 = 47.3 ...
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This note was uploaded on 07/30/2009 for the course ECE 3060 taught by Professor Shimmel during the Spring '07 term at Georgia Institute of Technology.

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