lec4MosEqns

lec4MosEqns - Introduction to CMOS VLSI Design MOS devices:...

Info iconThis preview shows pages 1–12. Sign up to view the full content.

View Full Document Right Arrow Icon
Introduction to CMOS VLSI Design MOS devices: static and dynamic behavior
Background image of page 1

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
MOS equations Slide 2 CMOS VLSI Design Outline DC Response Logic Levels and Noise Margins Transient Response Delay Estimation
Background image of page 2
MOS equations Slide 3 CMOS VLSI Design Activity 1) If the width of a transistor increases, the current will increase decrease not change 2) If the length of a transistor increases, the current will increase decrease not change 3) If the supply voltage of a chip increases, the maximum transistor current will increase decrease not change 4) If the width of a transistor increases, its gate capacitance will increase decrease not change 5) If the length of a transistor increases, its gate capacitance will increase decrease not change 6) If the supply voltage of a chip increases, the gate capacitance of each transistor will increase decrease not change
Background image of page 3

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
MOS equations Slide 4 CMOS VLSI Design Activity 1) If the width of a transistor increases, the current will increase decrease not change 2) If the length of a transistor increases, the current will increase decrease not change 3) If the supply voltage of a chip increases, the maximum transistor current will increase decrease not change 4) If the width of a transistor increases, its gate capacitance will increase decrease not change 5) If the length of a transistor increases, its gate capacitance will increase decrease not change 6) If the supply voltage of a chip increases, the gate capacitance of each transistor will increase decrease not change
Background image of page 4
MOS equations Slide 5 CMOS VLSI Design DC Response DC Response: V out vs. V in for a gate Ex: Inverter – When V in = 0 -> V out = V DD – When V in = V DD -> V out = 0 – In between, V out depends on transistor size and current By KCL, must settle such that I dsn = |I dsp | We could solve equations But graphical solution gives more insight I dsn I dsp V out V DD V in
Background image of page 5

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
MOS equations Slide 6 CMOS VLSI Design Transistor Operation Current depends on region of transistor behavior For what V in and V out are nMOS and pMOS in Cutoff? Linear? Saturation?
Background image of page 6
MOS equations Slide 7 CMOS VLSI Design nMOS Operation Cutoff Linear Saturated V gsn < V gsn > V dsn < V gsn > V dsn > I dsn I dsp V out V DD V in
Background image of page 7

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
MOS equations Slide 8 CMOS VLSI Design nMOS Operation Cutoff Linear Saturated V gsn < V tn V gsn > V tn V dsn < V gsn – V tn V gsn > V tn V dsn > V gsn – V tn I dsn I dsp V out V DD V in
Background image of page 8
MOS equations Slide 9 CMOS VLSI Design nMOS Operation Cutoff Linear Saturated V gsn < V tn V gsn > V tn V dsn < V gsn – V tn V gsn > V tn V dsn > V gsn – V tn I dsn I dsp V out V DD V in V gsn = V in V dsn = V out
Background image of page 9

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
MOS equations Slide 10 CMOS VLSI Design nMOS Operation Cutoff Linear Saturated V gsn < V tn V in < V tn V gsn > V tn V in > V tn V dsn < V gsn – V tn V out < V in - V tn V gsn > V tn V in > V tn V dsn > V gsn – V tn V out > V in - V tn I dsn I dsp V out V DD V in V gsn = V in V dsn = V out
Background image of page 10
MOS equations Slide 11 CMOS VLSI Design pMOS Operation Cutoff Linear Saturated V gsp > V gsp < V dsp > V gsp < V dsp < I dsn I dsp V out V DD V in
Background image of page 11

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Image of page 12
This is the end of the preview. Sign up to access the rest of the document.

This note was uploaded on 07/31/2009 for the course EE 577A taught by Professor Bhatti during the Spring '08 term at USC.

Page1 / 62

lec4MosEqns - Introduction to CMOS VLSI Design MOS devices:...

This preview shows document pages 1 - 12. Sign up to view the full document.

View Full Document Right Arrow Icon
Ask a homework question - tutors are online