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lec4MosEqns

# lec4MosEqns - Introduction to CMOS VLSI Design MOS devices...

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Introduction to CMOS VLSI Design MOS devices: static and dynamic behavior

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MOS equations Slide 2 CMOS VLSI Design Outline DC Response Logic Levels and Noise Margins Transient Response Delay Estimation
MOS equations Slide 3 CMOS VLSI Design Activity 1) If the width of a transistor increases, the current will increase decrease not change 2) If the length of a transistor increases, the current will increase decrease not change 3) If the supply voltage of a chip increases, the maximum transistor current will increase decrease not change 4) If the width of a transistor increases, its gate capacitance will increase decrease not change 5) If the length of a transistor increases, its gate capacitance will increase decrease not change 6) If the supply voltage of a chip increases, the gate capacitance of each transistor will increase decrease not change

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MOS equations Slide 4 CMOS VLSI Design Activity 1) If the width of a transistor increases, the current will increase decrease not change 2) If the length of a transistor increases, the current will increase decrease not change 3) If the supply voltage of a chip increases, the maximum transistor current will increase decrease not change 4) If the width of a transistor increases, its gate capacitance will increase decrease not change 5) If the length of a transistor increases, its gate capacitance will increase decrease not change 6) If the supply voltage of a chip increases, the gate capacitance of each transistor will increase decrease not change
MOS equations Slide 5 CMOS VLSI Design DC Response DC Response: V out vs. V in for a gate Ex: Inverter – When V in = 0 -> V out = V DD – When V in = V DD -> V out = 0 – In between, V out depends on transistor size and current By KCL, must settle such that I dsn = |I dsp | We could solve equations But graphical solution gives more insight I dsn I dsp V out V DD V in

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MOS equations Slide 6 CMOS VLSI Design Transistor Operation Current depends on region of transistor behavior For what V in and V out are nMOS and pMOS in Cutoff? Linear? Saturation?
MOS equations Slide 7 CMOS VLSI Design nMOS Operation Cutoff Linear Saturated V gsn < V gsn > V dsn < V gsn > V dsn > I dsn I dsp V out V DD V in

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MOS equations Slide 8 CMOS VLSI Design nMOS Operation Cutoff Linear Saturated V gsn < V tn V gsn > V tn V dsn < V gsn – V tn V gsn > V tn V dsn > V gsn – V tn I dsn I dsp V out V DD V in
MOS equations Slide 9 CMOS VLSI Design nMOS Operation Cutoff Linear Saturated V gsn < V tn V gsn > V tn V dsn < V gsn – V tn V gsn > V tn V dsn > V gsn – V tn I dsn I dsp V out V DD V in V gsn = V in V dsn = V out

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MOS equations Slide 10 CMOS VLSI Design nMOS Operation Cutoff Linear Saturated V gsn < V tn V in < V tn V gsn > V tn V in > V tn V dsn < V gsn – V tn V out < V in - V tn V gsn > V tn V in > V tn V dsn > V gsn – V tn V out > V in - V tn I dsn I dsp V out V DD V in V gsn = V in V dsn = V out
MOS equations Slide 11 CMOS VLSI Design pMOS Operation Cutoff Linear Saturated V gsp > V gsp < V dsp > V gsp < V dsp < I dsn I dsp V out V DD V in

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lec4MosEqns - Introduction to CMOS VLSI Design MOS devices...

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