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Computer Architecture

# Computer Architecture - Name Computer Architecture EE 4720...

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Name Computer Architecture EE 4720 Final Examination 8 May 2000, 10:00–12:00 CDT Alias Problem 1 (20 pts) Problem 2 (10 pts) Problem 3 (10 pts) Problem 4 (21 pts) Problem 5 (39 pts) Exam Total (100 pts) Good Luck!

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Problem 1: An extended DLX ISA, Triple-DLX [tm], includes new three-operand integer ALU in- structions. (Assume that the integer ALU can perform integer multiply.) Some sample instructions appear below: add_add r1, r2, r3, r4 ! r1 = r2 + r3 + r4 add_mul r5, r6, r7, r8 ! r5 = ( r6 + r7 ) * r8 mul_add r5, r6, r7, r8 ! r5 = ( r6 * r7 ) + r8 ( a ) (8 pts)A new instruction type, Type-T, will be used for these instructions. Show how the new Type-T instructions can be coded. The coding should be chosen to ease implementation and should allow for at least 64 three-operand instructions. Assume that there are six free opcode field values and seven free func-field values available for your use. Explain how to distinguish Type-T instructions from Type-R, Type-I, and Type-J in- structions. How many Type-T instructions can be provided using your coding? The DLX codings are given below for reference and can be used to explain your answer. Type R: Opcode 0 0 5 rs1 6 10 rs2 11 15 rd 16 20 func 21 31 Type I: Opcode 0 5 rs1 6 10 rd 11 15 Immediate 16 31 Type J: Opcode 0 5 Offset 6 31 2
( b ) Modify the pipeline below so that it can execute the three-operand instructions. A second ALU has been placed in the MEM stage; it should be used to help implement the instructions. The register file is among the parts that need to be modified. (6 pts) sign ext. IR Addr 6..10 11..15 16..20 or 11..15 IR IF ID EX WB MEM IR IR A B IMM NPC ALU =0 Addr Data Data Addr D In +4 PC Mem Port Addr Data Addr In Mem Out B ALU MD ( c ) Show a pipeline execution diagram for the code below assuming that all needed bypass paths are available. The code should execute as fast as possible. Add

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