Dynamic Scheduling

Dynamic Scheduling - 10-1 10-1 DynamicScheduling ThisSet

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Unformatted text preview: 10-1 10-1 DynamicScheduling ThisSet SchedulingandDynamicExecutionDefinitions FromvariouspartsofChapter4. DescriptionofTwoDynamicSchedulingMethods Notyetcomplete. (Materialbelowmayrepeatmaterialabove.) TomasulosAlgorithmBasics Section4.2 ReorderBufferandTomasulosAlgorithm Sections4.2and4.8plusnon-textmaterial. Non-textmaterial. SampleProblems 10-1 EE4720LectureTransparency.Formatted12:21,3May2004fromlsli10. 10-1 10-2 10-2 DynamicScheduling Scheduling: Organizinginstructionstoimproveexecutionefficiency. StaticScheduling: Organizingofinstructionsbycompilerorprogrammertoimproveexecutionefficiency. StaticallyScheduledProcessor: Aprocessorthatstartsinstructionsinprogramorder.Itachievesbetterperformanceoncode thathadbeenstaticallyscheduled.Processorscoveredinclassuptothispointwerestatically scheduled. DynamicScheduling: [processorimplementation] Aprocessorthatallowsinstructionstostartexecution ... ... evenifprecedinginstructionsarewaitingforoperands. Staticschedulingadvantage:timeandprocessingpoweravailabletoscheduler(part ofcompiler). Dynamicschedulingadvantage:canexecuteinstructionsafterloadsthatmissthe cache(theywilltakealongtimetocomplete).(Compilercannotoftenpredictload misses.)Canmakeupforbadorinappropriate(targetedwrongimplementation)static scheduling. 10-2 EE4720LectureTransparency.Formatted12:21,3May2004fromlsli10. 10-2 10-3 10-3 SchedulingExamples UnscheduledCode add.s f0,f1,f2 sub.sf3,f0,f4 mul.sf5,f6,f7 lwc1 f8,0(r1) addi r1,r1,8 ori r2,r2,1 10-3 EE4720LectureTransparency.Formatted12:21,3May2004fromlsli10. 10-3 10-4 10-4 UnscheduledCodeonStaticallyScheduled(HPChapter-3)MIPS Cycle: 1 2 3 4 5 6 7 8 9 10 11 add.s f0,f1,f2 IF ID A0 A1 A2 A3 WF sub.s f3,f0,f4 IF ID---------> A0 A1 A2 A3 WF mul.s f5,f6,f7 IF---------> ID M0 M1 M2 M3 M4 M5 M6 WF lwc1 f8,0(r1) IF ID-> EX MEMWF addi r1,r1,8 IF-> ID EX MEMWB ori r2,r2,1 IF ID EX MEMWB Executionhasfourstallcycles. 10-4 EE4720LectureTransparency.Formatted12:21,3May2004fromlsli10. 10-4 10-5 10-5 StaticallyScheduledCodeonStaticallyScheduledMIPSImplementation Instructionsreorderedbycompilerorprogrammertoremovestalls. Cycle: 1 2 3 4 5 6 7 8 9 10 11 add.s f0,f1,f2 IF ID A0 A1 A2 A3 WF lwc1 f8,0(r1) IF ID EX MEMWF mul.sf5,f6,f4 IF ID M0 M1 M2 M3 M4 M5 M6 WF addi r1,r1,8 IF ID EX MEMWB sub.s f3,f0,f4 IF ID A0 A1 A2 A3 WF ori r2,r2,1 IF ID EX MEMWB Executionhaszerostallcycles. 10-5 EE4720LectureTransparency.Formatted12:21,3May2004fromlsli10. 10-5 10-6 10-6 Executionofunscheduledcodeondynamicallyscheduledprocessor: Cycle: 1 2 3 4 5 6 7 8 9 10 11 add.s f0,f1,f2 IF ID Q RR A0 A1 A2 A3 WC sub.s f3,f0,f4 IF ID Q RR A0 A1 A2 A3 WC mul.sf5,f6,f7 IF ID Q RR M0 M1 M2 M3 M4 M5 M6 WC lwc1 f8,0(r1) IF ID Q RR EA MEMWB C addi r1,r1,8 IF ID Q RR EX WB C ori r2,r2,1 IF ID Q RR EX WB C Processordelays sub.s until f0 isavailable. Notethatinstructions start outoforder( mul.s before sub.s ) ... ... thisiscalled out-of-orderexecution . (Inthestaticallyscheduled(Chapter-3)implementationsFPinstructionsstartedin...
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Dynamic Scheduling - 10-1 10-1 DynamicScheduling ThisSet

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