{[ promptMessage ]}

Bookmark it

{[ promptMessage ]}

Dynamic Scheduling

Dynamic Scheduling - 10-1 Dynamic Scheduling 10-1 10-2...

Info icon This preview shows pages 1–3. Sign up to view the full content.

View Full Document Right Arrow Icon
Dynamic Scheduling This Set Scheduling and Dynamic Execution Definitions From various parts of Chapter 4. Description of Two Dynamic Scheduling Methods Not yet complete. (Material below may repeat material above.) Tomasulo’s Algorithm Basics Section 4.2 Reorder Buffer and Tomasulo’s Algorithm Sections 4.2 and 4.8 plus non-text material. Non-text material. Sample Problems EE 4720 Lecture Transparency. Formatted 12:21, 3 May 2004 from lsli10. Dynamic Scheduling Scheduling: Organizing instructions to improve execution efficiency. Static Scheduling: Organizing of instructions by compiler or programmer to improve execution efficiency. Statically Scheduled Processor: A processor that starts instructions in program order. It achieves better performance on code that had been statically scheduled. Processors covered in class up to this point were statically scheduled. Dynamic Scheduling: [processor implementation] A processor that allows instructions to start execution ... ... even if preceding instructions are waiting for operands. Static scheduling advantage: time and processing power available to scheduler (part of compiler). Dynamic scheduling advantage: can execute instructions after loads that miss the cache (they will take a long time to complete). (Compiler cannot often predict load misses.) Can make up for bad or inappropriate (targeted wrong implementation) static scheduling. EE 4720 Lecture Transparency. Formatted 12:21, 3 May 2004 from lsli10. Scheduling Examples Unscheduled Code add.s f0, f1, f2 sub.s f3, f0, f4 mul.s f5, f6, f7 lwc1 f8, 0(r1) addi r1, r1, 8 ori r2, r2, 1 EE 4720 Lecture Transparency. Formatted 12:21, 3 May 2004 from lsli10. Unscheduled Code on Statically Scheduled (HP Chapter-3) MIPS Cycle: 0 1 2 3 4 5 6 7 8 9 10 11 add.s f0, f1, f2 IF ID A0 A1 A2 A3 WF sub.s f3, f0, f4 IF ID ---------> A0 A1 A2 A3 WF mul.s f5, f6, f7 IF ---------> ID M0 M1 M2 M3 M4 M5 M6 WF lwc1 f8, 0(r1) IF ID -> EX MEM WF addi r1, r1, 8 IF -> ID EX MEM WB ori r2, r2, 1 IF ID EX MEM WB Execution has four stall cycles. EE 4720 Lecture Transparency. Formatted 12:21, 3 May 2004 from lsli10.
Image of page 1

Info icon This preview has intentionally blurred sections. Sign up to view the full version.

View Full Document Right Arrow Icon
Statically Scheduled Code on Statically Scheduled MIPS Implementation Instructions reordered by compiler or programmer to remove stalls. Cycle: 0 1 2 3 4 5 6 7 8 9 10 11 add.s f0, f1, f2 IF ID A0 A1 A2 A3 WF lwc1 f8, 0(r1) IF ID EX MEM WF mul.s f5, f6, f4 IF ID M0 M1 M2 M3 M4 M5 M6 WF addi r1, r1, 8 IF ID EX MEM WB sub.s f3, f0, f4 IF ID A0 A1 A2 A3 WF ori r2, r2, 1 IF ID EX MEM WB Execution has zero stall cycles. EE 4720 Lecture Transparency. Formatted 12:21, 3 May 2004 from lsli10. Execution of unscheduled code on dynamically scheduled processor: Cycle: 0 1 2 3 4 5 6 7 8 9 10 11 add.s f0, f1, f2 IF ID Q RR A0 A1 A2 A3 WC sub.s f3, f0, f4 IF ID Q RR A0 A1 A2 A3 WC mul.s f5, f6, f7 IF ID Q RR M0 M1 M2 M3 M4 M5 M6 WC lwc1 f8, 0(r1) IF ID Q RR EA MEM WB C addi r1, r1, 8 IF ID Q RR EX WB C ori r2, r2, 1 IF ID Q RR EX WB C Processor delays sub.s until f0 is available.
Image of page 2
Image of page 3
This is the end of the preview. Sign up to access the rest of the document.
  • Spring '08
  • Staff
  • Register renaming, Tomasulo algorithm, Out-of-order execution, rob, Reservation Station, Lecture Transparency

{[ snackBarMessage ]}

What students are saying

  • Left Quote Icon

    As a current student on this bumpy collegiate pathway, I stumbled upon Course Hero, where I can find study resources for nearly all my courses, get online help from tutors 24/7, and even share my old projects, papers, and lecture notes with other students.

    Student Picture

    Kiran Temple University Fox School of Business ‘17, Course Hero Intern

  • Left Quote Icon

    I cannot even describe how much Course Hero helped me this summer. It’s truly become something I can always rely on and help me. In the end, I was not only able to survive summer classes, but I was able to thrive thanks to Course Hero.

    Student Picture

    Dana University of Pennsylvania ‘17, Course Hero Intern

  • Left Quote Icon

    The ability to access any university’s resources through Course Hero proved invaluable in my case. I was behind on Tulane coursework and actually used UCLA’s materials to help me move forward and get everything together on time.

    Student Picture

    Jill Tulane University ‘16, Course Hero Intern