Final Examination

Final Examination - Name Solution Computer Architecture EE...

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Unformatted text preview: Name Solution Computer Architecture EE 4720 Final Examination 13 December 2005, 12:3014:30 CST Alias Out-of-order graduation? Problem 1 (15 pts) Problem 2 (20 pts) Problem 3 (17 pts) Problem 4 (15 pts) Problem 5 (33 pts) Exam Total (100 pts) Good Luck! Problem 1: The implementation of a version of MIPS with loop count instructions is shown below, these are the same instructions used in Homework 5. Instruction mtlc rt moves the contents of the rt register into a special loop count register, lc , and instruction mtlci immed moves a 16-bit immediate, immed , into lc . The loop-counted branch bclz is taken unless the lc register is zero, it also decrements lc . (In the diagram the upper input to the lc register is the data input and the lower input, we , is a write enable.) Three wires in the implementation are labeled ( A , B , and C ). Show the values present on those wires for each cycle of the illustrated execution of the program in the space provided. Leave a value blank if the value has no effect, assume that instructions before and after the illustrated code are nops. Note that two iterations of the loop are shown. (15 pts) # Cycle 1 2 3 4 5 6 7 8 mtlci 100 IF ID EX ME WB LOOP: bclz LOOP IF ID EX ME WB add r2, r2, r3 IF ID EX ME WB # (2nd iteration) bclz LOOP IF ID EX ME WB add r2, r2, r3 IF ID EX ME WB # Cycle 1 2 3 4 5 6 7 8 A: 1 2 2 0* 2* 0* <- SOLUTION B: 2 3 3* 3* <- SOLUTION C: 1 1 1 <- SOLUTION # Cycle 1 2 3 4 5 6 7 8 See next page for discussion of solution. format immed IR Addr 25:21 20:16 IF ID EX WB MEM rsv rtv IMM NPC ALU Addr Data Data Addr D In +1 PC Mem Port Addr Data Out Addr Data In Mem Port Data Out rtv ALU MD dst dst dst Decode dest. reg NPC = 30 2 "0" + 15:0 25:0 29:26 29:0 0 1 =0 -1 15:0 wlc Writes lc wlc wlc we lc 0 1 2 0 1 3 2 A Control Logic B C lcv lcv 2 Discussion of solution on previous page. The loop count branch examines the lc register (or a bypassed value) when it is in the ID stage. (If it examined it in a later stage the first branch would have to stall.) Control signal B selects whether the lc register itself is used, 1, or a value in EX, 2, in MEM, 3, or in WB, 0. Register lc is updated by bclz , mtlc , and mtlci , but to maintain precise exceptions the update is done in the WB stage. The new value for the lc register passes through the existing ID/EX.rtv latch, then goes through two new latches, EX/MEM.lcv and MEM/WB.lcv . Wire A controls an ID-stage mux that selects which value to send to the ID/EX.rtv latch. A 2 on A selects the rt value, this would be used for mtlc and also for existing type R and store instructions. A 1 selects the immediate, for mtlci , and a 0 selects the decremented lc value, for bclz . Signal C is the write-enable for the lc register....
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Final Examination - Name Solution Computer Architecture EE...

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