Final Examination03

Final Examination03 - Name Computer Architecture EE 4720...

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Name Computer Architecture EE 4720 Final Examination 14 May 2003, 15:00–17:00 CDT Alias Problem 1 (20 pts) Problem 2 (15 pts) Problem 3 (15 pts) Problem 4 (20 pts) Problem 5 (30 pts) Exam Total (100 pts) Good Luck!
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Problem 1: The execution of a MIPS code fragment on a dynamically scheduled machine is shown in the tables and in the labels on the diagram, both on the next page. The tables show the contents of the ID Register Map, Commit Register Map, and the Physical Register File at each cycle. The diagram shows the values on certain wires at certain cycles. For example, 4:65 means that at cycle 4 the labeled wire holds value 65. The following are functional unit segment labels: Load/store, L1 L2; ±oating-point add, A1 A2 A3 A4; ±oating-point multiply, M1 M2 M3 M4 M5 M6; integer, EX. The register maps handle both integer and ±oating-point registers. ( a ) Write a program consistent with these tables and labels.(12 pts) Show a pipeline execution diagram, be sure to show where each instruction commits. Choose consistent instructions. Choose consistent registers. If a register number cannot be determined, use a question mark. ( b ) Complete the tables on the next page as follows:(8 pts) Show where registers are added to, “]”, and removed from, “[”, the free list. Show the values on the line marked X in the illustration. 2
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Problem 1, continued: See previous page for instructions. 25:21 20:16 rsPR dst ID Reg. Map IR NPC +4 PC Mem Port Addr Data PC PC dst St: C,X 0,0 ROB # C,X Addr D In Reorder Buffer dst Control Control ROB # Op, IQ Common Data Bus (CDB) ROB # tail head ID IF rtPR Free List dstPR dstPR Instr. Queue Addr Addr Data Data Addr D In rsPR rtPR rsVal rtVal Physical Register File Op, dstPR, ROB# Out In Scheduler EX dstPR dstVal. Decode dest. reg incmb Addr Addr Data Data Addr D In D Out dst incmb dstPR Addr D In C Reg. Map Data incmb dstPR Recover Q 2:50, 3:65, 5:20, 6:93,10:59 10:93 3:12 4:65 X # Cycle 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 IF ID IF ID IF ID IF ID IF ID # Cycle 0 1 2 3
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This note was uploaded on 08/01/2009 for the course EE 4720 taught by Professor Staff during the Spring '08 term at LSU.

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Final Examination03 - Name Computer Architecture EE 4720...

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