Final Examination 00

Final Examination 00 - Name Solution Computer Architecture...

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Name Solution Computer Architecture EE 4720 Final Examination 8 May 2000, 10:00–12:00 CDT Alias MPL phone home!!! Problem 1 (20 pts) Problem 2 (10 pts) Problem 3 (10 pts) Problem 4 (21 pts) Problem 5 (39 pts) Exam Total (100 pts) Good Luck!
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Problem 1: An extended DLX ISA, Triple-DLX [tm], includes new three-operand integer ALU in- structions. (Assume that the integer ALU can perform integer multiply.) Some sample instructions appear below: add_add r1, r2, r3, r4 ! r1 = r2 + r3 + r4 add_mul r5, r6, r7, r8 ! r5 = ( r6 + r7 ) * r8 mul_add r5, r6, r7, r8 ! r5 = ( r6 * r7 ) + r8 ( a ) (8 pts)A new instruction type, Type-T, will be used for these instructions. Show how the new Type-T instructions can be coded. The coding should be chosen to ease implementation and should allow for at least 64 three-operand instructions. Assume that there are six free opcode Feld values and seven free func-Feld values available for your use. Explain how to distinguish Type-T instructions from Type-R, Type-I, and Type-J in- structions. How many Type-T instructions can be provided using your coding? The DLX codings are given below for reference and can be used to explain your answer. Type R: Opcode 0 0 5 rs1 6 10 rs2 11 15 rd 16 20 func 21 31 Type I: Opcode 0 5 rs1 6 10 rd 11 15 Immediate 16 31 Type J: Opcode 0 5 O±set 6 31 The instruction format is similar to Type R, except an rs3 Feld is added. It’s added after rd, rather than before, so that decoding logic would not have to look for rd in a third place. Type T instruction use one of the 6 opcodes, opcode 1 is used in the example. The funcette Feld, at 6 bits, speciFes which of 64 instructions to perform. Type T: Opcode 1 0 5 rs1 6 10 rs2 11 15 rd 16 20 rs3 21 25 funcette 26 31 2
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( b ) Modify the pipeline below so that it can execute the three-operand instructions. A second ALU has been placed in the MEM stage; it should be used to help implement the instructions. The register Fle is among the parts that need to be modiFed. (6 pts) Changes to the pipeline are shown in red bold. sign ext. IR Addr 6..10 11. .15 16. .20 or 11. .15 IR IF ID EX WB MEM IR IR A B IMM NPC ALU =0 Addr Data Data Addr D In +4 PC Mem Port Addr Data Addr In Mem Out B ALU MD Data Addr C C 21. .25 4 6 8 ( c ) Show a pipeline execution diagram for the code below assuming that all needed bypass paths are available. The code should execute as fast as possible. Add any needed bypass paths to the diagram above. Do not add any bypass paths that are not needed by the code below. Label each bypass path (added or already present) with the cycle in which it is used. Please be sure not to miss any true dependencies. (6 pts) The pipeline execution diagram is shown below. Note that the MEM stage has been labeled E2 to emphasize its role. Also note that in cycle 8 r6 is bypassed to the second ALU in the E2 (MEM) stage. The bypass paths and the cycles in which they are used are shown in blue in the illustration above.
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Final Examination 00 - Name Solution Computer Architecture...

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