Final Examination 97

Final Examination 97 - Name Computer Architecture EE 4720...

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Name Computer Architecture EE 4720 Final Examination 10 May 1997, 12:30–14:30 CDT Alias Problem 1 (25 pts) Problem 2 (25 pts) Problem 3 (25 pts) Problem 4 (25 pts) Exam Total (100 pts) Good Luck!
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Problem 1: DLX’s immediate instructions use 16-bit immediates. Because in many cases larger immediates are needed, new larger-immediate instructions are to be added to DLX. Larger- immediate instructions specify an integer arithmetic operation and an immediate, but no registers. The operation is performed using the immediate as one source and the most-recent destination register as both the other source and the destination. For example, consider larger-immediate instruction addli in the code fragment below: lw r6, 0(r7) sub r1, r2, r3 sw 0(r4), r5 addli #0x1ffff ! Operation: r1 = r1 + 0x1ffff The addli instruction uses r1 because it was the most-recent destination register used. (The sw does not modify r4 or r5 , so they aren’t used. The lw does modify r6 , but it is executed before the sub .) The larger-immediate instructions use the J-type format: a 6-bit opcode followed by a 26-bit immediate. ( a ) Let register r10 hold the memory address of an integer. The sum of that integer and 0x981234 is to be written to r11 . Write two code fragments to perform this operation, one with and one without a larger-immediate instruction. (5 pts) 2
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Problem 1 continued: ( b ) Show the modifications needed to implement larger-immediate in- structions on the pipeline illustrated below. (Read the next part before solving.) (10 pts) ( c ) Show how bypassing can be implemented for the instruction. (Hint: This is easier than regular bypassing since one source is the most-recent destination.) (10 pts) Addresses must be presented to the register file at the beginning of a cycle and the data won’t be available until the end of the cycle. Be sure to label the function of each connection to registers and other devices. ( E.g. , address, write, data.) Avoid magic boxes and clouds. Explain your modifications using an annotated timing diagram showing sample code executing. A detailed logic and timing diagram are preferred over a lengthy verbal description. X3DX30 X49X52 X49X52 X49X4DX4D X41X64X64X72 X41X64X64X72 X41X64X64X72 X44X61X74X61 X44X61X74X61 X44X61X74X61X20X49X6E X41 X42 X41X4CX55 X53 X49X47X4E X45X58X54 X36X2EX2EX31X30 X31X31X2EX2EX31X35 X31X36X2EX2EX33X31 X49X52 X4EX50X43 X4EX50X43 X50X43 X4DX65X6DX6FX72X79X20X50X6FX72X74 X41X64X64X72 X44X61X74X61 X34
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