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Unformatted text preview: EE 4720 Homework 3 Due: 2 October 2000 Problem 1: What changes would have to be made to the pipeline below to add the DLX-BAM indexed addressing instructions (from homework 2). Hint: The load is easy and inexpensive, the store requires a substantial change. Add the changes to the diagram below, but omit the control logic. Do explain how the control logic would have to be changed. ! Indexed addressing. lw r1, (r2+r3) ! r1 = MEM[ r2 + r3 ]; sw (r2+r3), r4 ! MEM[ r2 + r3 ] + r4; sign ext. IR Addr 6..10 11..15 16..20 or 11..15 IR IF ID EX WB MEM IR IR A B IMM NPC ALU =0 Addr Data Data Addr D In +4 PC Mem Port Addr Data Addr In Mem Out B ALU MD Problem 2: For maximum pedagogical benefit solve the problem above before attempting this one. The integer pipeline of the Sun Microsystems microSPARC-IIep implementation of the SPARC V8 ISA is similar to the Chapter-3 implementation of DLX that is being covered in class. What are the stage names and abbreviations used in the microSPARC-IIep? Hint: This is really easy once you’ve found the right page. SPARC V8 includes indexed addressing, for example: ld [%o3+%o0], %o2 ! Load word: %o2 = MEM[ %o3 + %o0 ] st %o0, [%o1+%g1] ! Store word: MEM[ %o1 + %g1 ] = %o0 (Register %o0 is a real register, not a special zero register.) What are the differences between the micro-a special zero register....
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This note was uploaded on 08/01/2009 for the course EE 4720 taught by Professor Staff during the Spring '08 term at LSU.
- Spring '08