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Unformatted text preview: EE 4720 Homework 3 Solution Due: 2 October 2000 Problem 1: What changes would have to be made to the pipeline below to add the DLX-BAM indexed addressing instructions (from homework 2). Hint: The load is easy and inexpensive, the store requires a substantial change. Add the changes to the diagram below, but omit the control logic. Do explain how the control logic would have to be changed. ! Indexed addressing. lw r1, (r2+r3) ! r1 = MEM[ r2 + r3 ]; sw (r2+r3), r4 ! MEM[ r2 + r3 ] + r4; No datapath changes are needed to implement the indexed load. The control logic must recognize the new instruction type and use the A and B inputs to the ALU rather than the A and IMM that are used for ordinary loads. The changes needed to implement the indexed store are shown in red bold below. A third read port is added to the register file in ID and a multiplexor is added to route either the ID/EX.B or the new ID/EX.C latch to the memory data in in the MEM stage. Control logic changes are similar to the indexed load, with the addition of control for the new multiplexor. sign ext. IR Addr 6..10 11..15 16..20 or 11..15 IR IF ID EX WB MEM IR IR A B IMM NPC ALU =0 Addr Data Addr D In +4 PC Mem Port Addr Data Addr In Mem Out BC ALU MD Addr Data Data 16..20 C Problem 2: For maximum pedagogical benefit solve the problem above before attempting this one. The integer pipeline of the Sun Microsystems microSPARC-IIep implementation of the SPARC V8 ISA is similar to the Chapter-3 implementation of DLX that is being covered in class. What are the stage names and abbreviations used in the microSPARC-IIep? Hint: This is really easy once you’ve found the right page. SPARC V8 includes indexed addressing, for example: ld [%o3+%o0], %o2 ! Load word: %o2 = MEM[ %o3 + %o0 ] st %o0, [%o1+%g1] ! Store word: MEM[ %o1 + %g1 ] = %o0 (Register %o0 is a real register, not a special zero register.) What are the differences between the micro-a special zero register....
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- Spring '08