Homework4 04

Homework4 04 - LSU EE 4720 Problem 1: Homework 4 Solution...

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LSU EE 4720 Homework 4 Solution Due: 22 March 2004 Problem 1: Suppose code like the memory copy program below (from Homework 3) appears frequently enough in the execution of programs so that new instructions should be added to the ISA to allow improved execution. (It does and they have been.) Following the points below devise new instruction(s) that can be used to write a new memory copy loop that would execute more e±ciently than is possible with existing MIPS-I instructions. A goal is to copy at the rate of two bytes per cycle. See the subparts after the bulleted points below. The instructions must use the existing MIPS formats. An instruction can do more than one thing (as long as it follows the points below). For example, an instruction that does more than one thing is a post-increment load. To reach the two bytes / cycle limit one might need to combine a branch with something. The instructions cannot use implicit registers. (A register is implicit if it does not appear in the encoded instruction. For example, register 31 is implicit in the jal instruction.) To achieve two bytes per cycle the instructions might need to do something unusual with operands. Please ask if you’re not sure if something is too unusual. As with all other ordinary instructions, the new instructions must advance one stage per cycle (unless stalled, if so they would sit idle).
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This note was uploaded on 08/01/2009 for the course EE 4720 taught by Professor Staff during the Spring '08 term at LSU.

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Homework4 04 - LSU EE 4720 Problem 1: Homework 4 Solution...

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