Homework5 01

Homework5 01 - EE 4720 Homework 5 Due: 5 December 2001...

Info iconThis preview shows pages 1–2. Sign up to view the full content.

View Full Document Right Arrow Icon

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: EE 4720 Homework 5 Due: 5 December 2001 Problem 1: An ISA has a character size of c = 9 bits (one more than most other ISA’s!) and a 30-bit address space ( A ). An implementation has a bus width of w = 72 bits and has no cache. Show how 2 20 × 36 memory devices can be connected to implement the entire address space for this implementation. Show only the connections needed for loads. Show the alignment network as a box. Label inputs and outputs and be sure to specify which address bits are being used. The solution will require many memory devices so use ellipses ( · · · ) between the first and last of a large group of items. Problem 2: The program below computes the sum of an array of doubles and also computes the sum of the characters in the array. The system uses a direct-mapped cache consisting of 1024 lines with a line size of 256 bits. void p3(double *dstart, double *dend) { double dsum = 0.0; int csum = 0; double *d = dstart; // sizeof(double) = 8 characters unsigned char *c = (unsigned char *) dstart; // A character is 8 bits. unsigned char *cend = (unsigned char *) dend; int dlength = dend - d; int clength = cend - c; while( d < dend ) dsum += *d++; if( ! LAST_PART ) flush_the_cache(); // Removes all data from the cache....
View Full Document

This note was uploaded on 08/01/2009 for the course EE 4720 taught by Professor Staff during the Spring '08 term at LSU.

Page1 / 2

Homework5 01 - EE 4720 Homework 5 Due: 5 December 2001...

This preview shows document pages 1 - 2. Sign up to view the full document.

View Full Document Right Arrow Icon
Ask a homework question - tutors are online