Homework5 01

Homework5 01 - EE 4720 Problem 1 Homework 5 Due 5 December...

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An ISA has a character size of c = 9 bits (one more than most other ISA’s!) and a 30-bit address space ( A ). An implementation has a bus width of w = 72 bits and has no cache. Show how 2 20 × 36 memory devices can be connected to implement the entire address space for this implementation. Show only the connections needed for loads. Show the alignment network as a box. Label inputs and outputs and be sure to specify which address bits are being used. The solution will require many memory devices so use ellipses ( · · · ) between the first and last of a large group of items. The program below computes the sum of an array of doubles and also computes the sum of the characters in the array. The system uses a direct-mapped cache consisting of 1024 lines with a line size of 256 bits. void p3(double *dstart, double *dend) { double dsum = 0.0; int csum = 0; double *d = dstart; // sizeof(double) = 8 characters unsigned char *c = (unsigned char *) dstart; // A character is 8 bits. unsigned char *cend = (unsigned char *) dend; int dlength = dend - d; int clength = cend - c; while( d < dend ) dsum += *d++; if( ! LAST_PART ) flush_the_cache(); // Removes all data from the cache. while( c < cend ) csum += *c++; } When the procedure is called none of the data in the array is cached. When answering the questions below consider only memory accesses needed for the array (double or character). Assume
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