Homework 2 05

Homework 2 05 - LSU EE 4720 Homework 2 Solution Due: 9...

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LSU EE 4720 Homework 2 Solution Due: 9 March 2005 For answers to the questions below refer to the PowerPC description Book I which can be found on the class references page, http://www.ece.lsu.edu/ee4720/reference.html . Problem 1: One instruction that MIPS lacks but many RISC ISAs have is an indexed load. Find the closest equivalent PowerPC instruction to SPARC’s lw [%r2+%r3],%r1 . ( a ) Show the instruction in PowerPC assembly language. # Solution: lwzx r1, r2, r3 Note: Instruction ldx , which loads 64 bits) would also be graded correct, but since SPARC’s lw is a 32-bit unsigned load (in SPARC V9), PPC’s 32-bit unsigned indexed load, lwzx , is more correct. ( b ) Show how the instruction is coded, include the register numbers. Text: OPCD 31 0 5 RT 1 6 10 RA 2 11 15 RB 3 16 20 XO 23 21 30 1 31 31 Problem 2: One instruction that MIPS lacks but that a few other RISC ISAs have is autoin- crement addressing. PowerPC has an instruction that can be used for autoincrement addressing but is more powerful than the autoincrement addressing described in class. Find the PowerPC
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This note was uploaded on 08/01/2009 for the course EE 4720 taught by Professor Staff during the Spring '08 term at LSU.

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Homework 2 05 - LSU EE 4720 Homework 2 Solution Due: 9...

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