Homework 2 08

Homework 2 08 - LSU EE 4720 Homework 2 Solution Due: 29...

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Unformatted text preview: LSU EE 4720 Homework 2 Solution Due: 29 February 2008 For the answers to these questions look at the ARM Architecture Reference Manual linked to the course references page, http://www.ece.lsu.edu/ee4720/reference.html . Problem 1: The register fields in ARM instructions are four bits and so only 16 integer registers are accessible. The ISA manual describes ARM as having 32 integer registers, however many of them are only accessible in particular modes. An advantage of fewer registers is that extra bits are available in the instruction encoding, for example, ARM three-register instruction formats would have three more bits available than the MIPS type R format. Where in the ARM formats do you think these bits went? In your answer give the instruction field and its purpose. There should be no equivalent in MIPS. Every instruction format uses a cond (condition field), there is no counterpart to this in MIPS. The condition field is used to predicate instructions, that is, control whether or not an instruction has any effect....
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This note was uploaded on 08/01/2009 for the course EE 4720 taught by Professor Staff during the Spring '08 term at LSU.

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Homework 2 08 - LSU EE 4720 Homework 2 Solution Due: 29...

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