Homework 3 07

Homework 3 07 - LSU EE 4720 Homework 3 Solution Due: 15...

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LSU EE 4720 Homework 3 Solution Due: 15 October 2007 The problems below ask about VAX instructions, which were not yet covered in class. For information on these instructions see the VAX Macro and Instruction Set manual linked to the EE 4720 references page. Problem 1: The VAX locc instruction fnds the frst occurrence oF a character in a string (see example below). The frst operand specifes the character to fnd (A in the example), the second operand specifes the length oF the string (in register r2 ), and the third operand specifes the address oF the frst character oF the string (register r3 below). # Find first occurrence of 65 (ASCII A) in memory starting at # address r3 and continuing for the next r2 characters. locc #65, r2, (r3) ( a ) Show how the sample instruction above is encoded. Include the name oF each feld and its value for the example above, not for the general case . In the original assignment the third argument was shown as r3 , not (r3) which is correct. Solution appears below. Note that “PC-addressing” is used to specify the constant 65. The name PC-addressing in this case is misleading since the PC is not used, it’s just that PC-addressing is what’s used to specify constants larger than six bits. SOLUTION: Instruction: locc #65, r2, (r3) Syntax: locc char.rb, len.rw, addr.ab Sections: opcode immediate_mode_op register_mode_op register_deferred_op opcode -> 8 bits: 0x3a immediate_mode_op -> operand_specifier immediate operand_specifier -> mode(=immediate) reg(=PC) -> (4 bits) 0x8 (4 bits) 0xf immediate -> (8 bits) 0x41 register_mode_op -> operand_specifier -> mode(=register) reg(=2) -> 0x5 0x2 register_deferred_op -> operand_specifier -> mode(=register deferred) reg_num(=3) -> 0x6 0x3 Instruction Encoding: -opcode- -- 1st operand ---- -- 2nd op - -- 3rd op - locc imm PC* 65 reg r2 reg-d r3 mode mode mode 0x3a 0x8 0xf 0x41 0x5 0x2 0x6 0x3 <- Encoded value. 7 0 7 4 3 0 7 0 7 4 3 0 7 4 3 0 <- Bit position.
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( b ) Provide an example of locc in which the encoded second and third operands each require more space than the example above. At least one of these operands should use a memory addressing mode that is not available in MIPS. Show the instruction in assembler and show its encoding. The second operand now uses byte displacement deferred (shown as bdd below), and the third operand uses absolute addressing. .data STR_ADDR: # Assume address is 0x1234 .asciiz "My string." .text locc #65, @B^8(r2), @#STR_ADDR opcode -- 1st operand ---- -- 2nd op ------- -- 3rd op -------------- locc imm 65 bdd r2 8 abs 32-bit mode mode mode constant 0x3a 0x8 0xf 0x41 0xb 0x2 0x8 0x9 0xf 0x1234 7 0 7 4 3 0 7 0 7 4 3 07 0 7 4 3 0 31 0
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This note was uploaded on 08/01/2009 for the course EE 4720 taught by Professor Staff during the Spring '08 term at LSU.

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Homework 3 07 - LSU EE 4720 Homework 3 Solution Due: 15...

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