Homework 3 s08

Homework 3 s08 - LSU EE 4720 Homework 3 Due: 29 October...

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Homework 3 Due: 29 October 2008 Problem 1: Two MIPS implementations appear below, the frst is the one presented in class, it will be called the mux-in-EX implementation . The second, the mux-in-ID implementation , has the ALU input multiplexers in the ID stage, to better balance critical paths. The clock Frequency oF the mux-in-EX implementation is 1 GHz and the clock Frequency oF the mux-in-ID implementation is 1 . 1 GHz. format immed IR Addr 25:21 20:16 IF ID EX WB ME rsv rtv IMM NPC ALU Addr Data Data Addr D In +1 PC Mem Port Addr Data Out Addr Data In Mem Port Data Out rtv ALU MD dst dst dst Decode dest. reg NPC = 30 2 2’b0 + 15:0 25:0 29:26 29:0 0 1 15:0 format immed IR Addr 25:21 20:16 IF ID EX WB ME NPC ALU Addr Data Data Addr D In +1 PC Mem Port Addr Data Out Addr Data In Mem Port Data Out rtv ALU MD dst dst Decode dest. reg a l u 1 = 30 2 2’b0 + 15:0 25:0 29:26 29:0 0 1 15:0 alu1 alu2 dst NPC ( a ) With this change some oF the ALU multiplexer inputs are unnecessary. Show which inputs are
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Homework 3 s08 - LSU EE 4720 Homework 3 Due: 29 October...

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