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LSUEE4720

# LSUEE4720 - LSU EE 4720 Problem 1 Cycle add \$t1 \$t2 \$t3 sub...

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Solution Consider the code below. # Cycle 0 1 add \$t1, \$t2, \$t3 IF ID sub \$t4, \$t5, \$t1 lw \$t6, 4(\$t1) sw 0(\$t4), \$t6 ( a ) Show a pipeline execution diagram for the code running on the following illustration. Note that the add is fetched in cycle zero. Take great care in determining the number of stall cycles. # Solution # # Cycle 0 1 2 3 4 5 6 7 8 9 10 11 add \$t1, \$t2, \$t3 IF ID EX ME WB sub \$t4, \$t5, \$t1 IF ID ----> EX ME WB lw \$t6, 4(\$t1) IF ----> ID EX ME WB sw 0(\$t4), \$t6 IF ID ----> EX ME WB format immed IR Addr 25:21 20:16 IR IF ID EX WB MEM IR IR rsv rtv IMM NPC ALU Addr Data Data Addr D In +4 PC Mem Port Addr Data Out Addr Data In Mem Port Data Out rtv ALU MD dst dst dst Decode dest. reg = =0 <0 E Z N NPC

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The code below is the same as in the previous problem. # Cycle 0 1 add \$t1, \$t2, \$t3 IF ID sub \$t4, \$t5, \$t1 lw \$t6, 4(\$t1) sw 0(\$t4), \$t6 ( a ) Show a pipeline execution diagram (PED) of the code running on the system below. # Cycle 0 1 2 3 4 5 6 7 8 9 add \$t1, \$t2, \$t3 IF ID EX (ME) (WB) sub \$t4, \$t5, \$t1 IF ID EX ME WB lw \$t6, 4(\$t1) IF ID EX ME WB sw 0(\$t4), \$t6 IF ID ------> EX ME WB ( b ) In the PED circle each stage that sends a bypassed value. In the diagram label each bypass path with the cycle in which it is used. To avoid ambiguity, label the end of the path (at the mux input). In the PED parenthesis are used instead of circles. format immed IR Addr 25:21 20:16 IR IF ID EX WB MEM IR IR rsv rtv IMM NPC ALU Addr Data Data Addr D In +4 PC Mem Port Addr Data Out Addr Data In Mem Port Data Out rtv ALU MD dst dst dst Decode dest. reg NPC 3 4
The problem below is tricky. If necessary use Spring 2001 Homework 2 problem 3 for

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LSUEE4720 - LSU EE 4720 Problem 1 Cycle add \$t1 \$t2 \$t3 sub...

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