LSUEE4720pipelin lecture

LSUEE4720pipelin lecture - 09-1 09-1 MaterialCovered...

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Unformatted text preview: 09-1 09-1 MulticyclePipelineOperations Materialmaybeaddedtothisset. MaterialCovered Section3.7. Long-LatencyOperations(Topics) Typicallong-latencyinstructions:floatingpoint Pipelinedv.non-pipelinedexecutionunits Initiationintervalandlatency Implementationoflong-latencyinstructions. Timingdiagrams 09-1 EE4720LectureTransparency.Formatted12:37,9November2003fromlsli09. 09-1 09-2 09-2 Long-LatencyInstructions(Operations) CommonLong-LatencyInstructions Fastest(shortest—butstilllong—latency):Floating-PointAdd,Subtract,Conversions MIPS: add.d , sub.d , cvt.s.w (convertintegertofloat),etc. IntermediateSpeed:Multiply MIPS: mul.d , mul.s . SlowestSpeed:Divide,Modulo,SquareRoot MIPS: div.d , sqrt.d . 09-2 EE4720LectureTransparency.Formatted12:37,9November2003fromlsli09. 09-2 09-3 09-3 ImplementationofLong-LatencyInstructions Implementationbalancescostandperformance. LowCost:Unpipelined,SingleFunctionalUnit,DataRecirculates Wholefunctionalunitoccupiedbyinstructionduringcomputation ... ... soitcanexecuteonlyoneinstructionatatime. IntermediateCost:MultipleUnpipelinedFunctionalUnits Functionalunitsoccupiedbyinstructionduringcomputation ... ... eachcanexecuteadifferentinstruction. Costamultipleofsingle-unitcost. HighestCost:PipelinedFunctionalUnit Functionalunitpipelined,atbesteachstagecanholdadifferentinstruction. Costdisadvantagedependsonhowunpipelinedunitsimplemented. 09-3 EE4720LectureTransparency.Formatted12:37,9November2003fromlsli09. 09-3 09-4 09-4 FloatingPointinChapter-3MIPSImplementation TypicalClassroomExampleFloatingPointFunctionalUnits • FPAdd Fourstages,fullypipelined:Latency3,InitiationInterval1. UsedforFPAdd,FPSubtract,FPComparisons,etc. • FPMultiply Sevenstages,fullypipelined:Latency6,InitiationInterval1. UsedforFPMultiplyandIntegerMultiply. • FPDivide Twentyfivestages,unpipelined:Latency24,InitiationInterval24. 09-4 EE4720LectureTransparency.Formatted12:37,9November2003fromlsli09. 09-4 09-5 09-5 Floating-PointPipeline Examplefloatingunitimplementationmainfeatures: Separateregisterfile. Numberofstagesvarydependingonfunctionalunit. Floating-pointwritebackseparatefromintegerwriteback. format immed IR Addr 25:21 20:16 IR IF EX WB MEM IR IR rsv rtv IMM NPC ALU Addr Data Data Addr D In +4 PC Mem Port Addr Data Out Addr Data In Mem Port Data Out rtv ALU MD dst dst dst Decode dest. reg NPC A1 Int Reg File FP Reg File fd fd fd FPU WF ID Addr Data D In WE Addr Addr Data fsv ftv 15:11 20:16 M1 A2 M2 M6 fd A4 we we we we Decode dest. reg Decode FPR write Add passes through four stages, mult through six. ID 09-5 EE4720LectureTransparency.Formatted12:37,9November2003fromlsli09. 09-5 09-6 09-6 Floating-PointPipeline format immed IR Addr 25:21 20:16 IR IF EX WB MEM IR IR rsv rtv IMM NPC ALU Addr Data Data Addr D In +4 PC Mem Port Addr Data Out Addr Data In Mem Port Data Out rtv ALU MD dst dst dst Decode dest. reg NPC A1 Int Reg File FP Reg File fd fd fd FPU WF ID Addr Data D In WE Addr Addr Data fsv ftv 15:11 20:16 M1 A2 M2 M6 fd A4 we we we we Decode...
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  • Spring '08
  • Staff
  • Pallavolo Modena, Bucharest Metro, M0 motorway, Motorways in Hungary, Lecture Transparency, Functional Unit Structural Hazards

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LSUEE4720pipelin lecture - 09-1 09-1 MaterialCovered...

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