This preview has intentionally blurred sections. Sign up to view the full version.View Full Document
Unformatted text preview: Name Solution Computer Architecture EE 4720 Midterm Examination 22 March 2000, 13:40–14:30 CST Alias Problem 1 (35 pts) Problem 2 (20 pts) Problem 3 (45 pts) Exam Total (100 pts) Good Luck! Problem 1: The DLX implementation below has six stages. (The work done by ID is now done by ID and RR.) sign ext. Addr 6..10 11..15 16..20 or 11..15 IR RR EX WB MEM IR IR A B IMM ALU =0 Addr Data Data Addr D In Addr In Mem Out B ALU MD NPC IR IF NPC +4 PC Mem Port Addr Data IR NPC IMM Control ID 4 5,6 6 ( a ) The execution of some code on this pipeline is shown below. Add exactly the bypass paths needed so that the code executes as illustrated. Next to each bypass path indicate the cycle(s) in which it will be used. (Do not add bypass paths that won’t be used in the execution of the code below.) (10 pts) ! Cycle 1 2 3 4 5 6 7 8 add r1, r2, r3 IF ID RR EX ME WB lw r5, 10(r1) IF ID RR EX ME WB xor r4, r1, r2 IF ID RR EX ME WB and r6, r5, r4 IF ID RR EX ME WB The changes are shown in the diagram above in blue bold. ( b ) Show the execution of the code below on this pipeline until bneq reaches IF a second time. The branch is taken. Be sure to base the CTI behavior on the hardware shown above. Show where instructions are squashed. (10 pts) The RR stage adds a cycle of branch penalty, but one cycle is saved, compared to the original pipelined DLX implemen- tation, because the ALU output, rather than the EX/MEM.ALU latch, is fed back to the PC multiplexor. LOOP: ! Solution. ! Cycle 1 2 3 4 5 6 7 8 bneq r1, SKIP IF ID RR EX ME WB IF add r2, r3, r4 IF ID RRx sub r5, r6, r7 IF IDx and r8, r9, r10 IFx or r11, r12, r13 SKIP: j LOOP IF ID RR EX ME add r2, r3, r4 IF ID RRx sub r5, r6, r7 IF IDx and r8, r9, r10 IFx or r11, r12, r13 2 Problem 1, continued:...
View Full Document
- Spring '08
- SEPTA Regional Rail, Rs Rs, Rs Rs Rs, Arch. Reg, ID RS RS, RS RS ID